74LVQ125M ,QUAD BUS BUFFERS (3-STATE)Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LVQ138 ,3 TO 8 LINE DECODER (INVERTING)Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
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74LVQ138TTR ,3 TO 8 LINE DECODER (INVERTING)74LVQ1383 TO 8 LINE DECODER (INVERTING) ■ HIGH SPEED: t = 5.5ns (TYP.) at V = 3.3 VPD CC■ COMPATIB ..
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74LVQ125M
QUAD BUS BUFFERS (3-STATE)
1/9July 2001 HIGH SPEED:
tPD = 5 ns (TYP.) at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION:
ICC = 4 μA (MAX.) at TA=25°C LOW NOISE:
VOLP = 0.3V (TYP .) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:OH| = IOL = 12mA (MIN) at VCC = 3.0 V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS:PLH ≅ tPHL OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74LVQ125 is a low voltage CMOS QUAD
BUS BUFFERS fabricated with sub-micron silicon
gate and double-layer metal wiring C2 MOS
technology. It is ideal for low power and low noise
3.3V applications.
The device requires the same 3-STATE control
input G to be set high to place the output in to the
high impedance state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ125LOW VOLTAGE QUAD BUS BUFFERS (3-STATE)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74LVQ1252/9
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don‘t Care
Z : High Impedance
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS 1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2V
74LVQ1253/9
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
DYNAMIC SWITCHING CHARACTERISTICS 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
74LVQ1254/9
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per gate)
74LVQ1255/9
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74LVQ1256/9
WAVEFORM 1 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
