74LVC573A ,Octal Transparent D-Type Latch with 3-State OutputsAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LVC573ATTR ,OCTAL D-TYPE LATCH HIGH PERFORMANCEAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LVC652 ,Octal transceiver/register with dual enable 3-State
74LVC74A ,positive-edge trigger
74LVC74A ,positive-edge trigger
74LVC74A ,positive-edge trigger
82541ER , 82541ER Gigabit Ethernet Controller
8255A , Programmable Peripheral Interface iAPX86 Family
8255A-5 , Programmable Peripheral Interface iAPX86 Family
82B715 ,I2C bus extender
82C11 , VOLTAGE DETECTORS
82C206 , NEW ENHANCED AT DATA BOOK
74LVC573A
Octal Transparent D-Type Latch with 3-State Outputs
1/13July 2004 5V TOLERANT INPUTS HIGH SPEED: tPD = 6.8ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 1.65V to 3.6V (1.2V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTIONThe 74LVC573A is a low voltage CMOS OCTAL
D-TYPE LATCH fabricated with sub-micron silicon
gate and double-layer metal wiring C2 MOS
technology. It is ideal for 1.65 to 3.6 VCC
operations and low power and low noise
applications.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q outputs
will be latched precisely or inversely at the logic
level of D input data. While the (OE) input is low,
the 8 outputs will be in a normal logic state (high or
low logic level) and while high level the outputs will
be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components. It has more speed performance at
3.3V than 5V AC/ACT family, combined with a
lower power consumption.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
74LVC573AOCTAL D-TYPE LATCH
HIGH PERFORMANCE
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes Rev. 3
74LVC573A2/13
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description Table 3: Truth Table X : Don’t Care
Z : High Impedance
Table 4: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
74LVC573A3/13
Table 5: Recommended Operating Conditions 1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
Table 6: DC Specifications
74LVC573A4/13
Table 7: Dynamic Switching Characteristics 1) Number of output defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
Table 8: AC Electrical Characteristics 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|
2) Parameter guaranteed by design
74LVC573A5/13
Table 9: Capacitive Characteristics 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
Figure 3: Test Circuit RT = ZOUT of pulse generator (typically 50Ω)
Table 10: Test Circuit And Waveform Symbol Value
74LVC573A6/13
Figure 4: Waveform - Propagation Delay, Setup And Hold Times (f=1MHz; 50% duty cycle)
Figure 5: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle)
74LVC573A7/13
Figure 6: Waveform - Propagation Delay Time (f=1MHz; 50% duty cycle)
