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74LVC3G14DP ,Triple inverting Schmitt trigger with 5 V tolerant inputGeneral descriptionThe 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is ..
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74LVC3G14DP
Triple inverting Schmitt trigger with 5 V tolerant input
1. General description
The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of
transforming slowly changing input signals into sharply defined, jitter-free output signals.
The inputs can be driven from either 3.3Vor5 V devices. This feature allows the use of
this device in a mixed 3.3V and5 V environment. Schmitt trigger action at the inputs
makes the circuit tolerant of slower input rise and fall time. This device is fully specified for
partial power-down applications using IOFF. The IOFF circuitry disables the output,
preventing the damaging backflow current through the device when it is powered down.
2. Features and benefits Wide supply voltage range from 1.65 V to 5.5V5 V tolerant input/output for interfacing with 5 V logic High noise immunity ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V 24 mA output drive (VCC =3.0V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Unlimited rise and fall times Multiple package options Specified from 40 C to +85 C and 40 C to +125 C.
3. Applications Wave and pulse shaper for highly noisy environment Astable multivibrator Monostable multivibrator.
74L VC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
Rev. 12 — 9 April 2013 Product data sheet
NXP Semiconductors 74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
4. Ordering information
5. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Table 1. Ordering information
74LVC3G14DP 40Cto +125C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74LVC3G14DC 40Cto +125C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74LVC3G14GT 40Cto +125C XSON8 plastic extremely thin small outline package; no leads; terminals; body 1  1.95  0.5 mm
SOT833-1
74LVC3G14GF 40 C to +125 C XSON8 extremely thin small outline package; no leads; terminals; body 1.351 0.5 mm
SOT1089
74LVC3G14GD 40Cto +125C XSON8 plastic extremely thin small outline package; no leads; terminals; body 3  2  0.5 mm
SOT996-2
74LVC3G14GM 40 C to +125C XQFN8 plastic, extremely thin quad flat package; no leads; terminals; body 1.6 1.6 0.5 mm
SOT902-2
74LVC3G14GN 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.2 1.0 0.35 mm
SOT1116
74LVC3G14GS 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.35 1.0 0.35 mm
SOT1203
Table 2. Marking codes
74LVC3G14DP V14
74LVC3G14DC V14
74LVC3G14GT V14
74LVC3G14GF VK
74LVC3G14GD V14
74LVC3G14GM V14
74LVC3G14GN VK
74LVC3G14GS VK
NXP Semiconductors 74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
6. Functional diagram
7. Pinning information
7.1 Pinning
NXP Semiconductors 74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
7.2 Pin description
8. Functional description
[1] H= HIGH voltage level; L= LOW voltage level
Table 3. Pin description
1A, 2A, 3A 1, 3, 6 7, 5, 2 data input , 2Y, 3Y 7, 5, 2 1, 3, 6 data output
GND 4 4 ground (0 V)
VCC 8 8 supply voltage
Table 4. Function table[1]
NXP Semiconductors 74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
9. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC=0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
10. Recommended operating conditions
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA output voltage Active mode [1][2] 0.5 VCC + 0.5 V
Power-down mode [1][2] 0.5 +6.5 V output current VO = 0 V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Ptot total power dissipation Tamb= 40 C to +125C [3]- 250 mW
Tstg storage temperature 65 +150 C
Table 6. Operating conditions
VCC supply voltage 1.65 5.5 V input voltage 0 5.5 V output voltage Active mode 0 VCC V
Power-down mode; VCC =0V 0 5.5 V
Tamb ambient temperature 40 +125 C
NXP Semiconductors 74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
11. Static characteristicsTable 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb = 40 C to +85C
VOH HIGH-level output voltage VI =VT+or VT
IO = 100 A; VCC = 1.65 V to 5.5 V VCC  0.1- - V
IO = 4 mA; VCC = 1.65 V 1.2 - - V
IO = 8 mA; VCC = 2.3 V 1.9 - - V
IO = 12 mA; VCC = 2.7 V 2.2 - - V
IO = 24 mA; VCC = 3.0 V 2.3 - - V
IO = 32 mA; VCC = 4.5 V 3.8 - - V
VOL LOW-level output voltage VI =VT+or VT
IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V
IO = 4 mA; VCC = 1.65 V - - 0.45 V
IO = 8 mA; VCC = 2.3 V - - 0.3 V
IO = 12 mA; VCC = 2.7 V - - 0.4 V
IO = 24 mA; VCC = 3.0 V - - 0.55 V
IO = 32 mA; VCC = 4.5 V - - 0.55 V input leakage current VI= 5.5Vor GND; VCC= 0 V to 5.5V - 0.1 5 A
IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - 0.1 10 A
ICC supply current VI= 5.5 Vor GND; IO =0A;
VCC= 1.65 V to 5.5 V
-0.1 10 A
ICC additional supply current VI = VCC  0.6 V; IO = 0A;
VCC= 2.3Vto 5.5 V 500 A input capacitance VCC= 3.3 V; VI = GND to VCC -3.5 -pF
Tamb = 40 C to +125C
VOH HIGH-level output voltage VI =VT+or VT
IO = 100 A; VCC = 1.65 V to 5.5 V VCC  0.1- - V
IO = 4 mA; VCC = 1.65 V 0.95 - - V
IO = 8 mA; VCC = 2.3 V 1.7 - - V
IO = 12 mA; VCC = 2.7 V 1.9 - - V
IO = 24 mA; VCC = 3.0 V 2.0 - - V
IO = 32 mA; VCC = 4.5 V 3.4 - - V
VOL LOW-level output voltage VI =VT+or VT
IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V
IO = 4 mA; VCC = 1.65 V - - 0.7 V
IO = 8 mA; VCC = 2.3 V - - 0.45 V
IO = 12 mA; VCC = 2.7 V - - 0.6 V
IO = 24 mA; VCC = 3.0 V - - 0.8 V
IO = 32 mA; VCC = 4.5 V - - 0.8 V input leakage current VI= 5.5Vor GND; VCC= 0 V to 5.5V - - 20 A
NXP Semiconductors 74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
[1] All typical values are measured at maximum VCC and Tamb = 25 C.
[1] All typical values are measured at Tamb = 25 C
[2] VH = VT+ VT
IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - 20 A
ICC supply current VI= 5.5 Vor GND; IO =0A;
VCC= 1.65 V to 5.5 V 40 A
ICC additional supply current VI = VCC  0.6 V; IO = 0A;
VCC= 2.3Vto 5.5 V - 5000 A
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Table 8. Transfer characteristics
Voltages are referenced to GND (ground=0 V; for test circuit see Figure9
VT+ positive-going
threshold voltage
see Figure 10 and
Figure11
VCC = 1.8 V 0.70 1.10 1.50 0.70 1.70 V
VCC = 2.3 V 1.00 1.40 1.80 1.00 2.00 V
VCC = 3.0 V 1.30 1.76 2.20 1.30 2.40 V
VCC = 4.5 V 1.90 2.47 3.10 1.90 3.30 V
VCC = 5.5 V 2.20 2.91 3.60 2.20 3.80 V
VT negative-going
threshold voltage
see Figure 10 and
Figure11
VCC = 1.8 V 0.25 0.61 0.90 0.25 1.10 V
VCC = 2.3 V 0.40 0.80 1.15 0.40 1.35 V
VCC = 3.0 V 0.60 1.04 1.50 0.60 1.70 V
VCC = 4.5 V 1.00 1.55 2.00 1.00 2.20 V
VCC = 5.5 V 1.20 1.86 2.30 1.20 2.50 V
VH [2] hysteresis voltage see Figure 10, Figure11
and Figure12
VCC = 1.8 V 0.15 0.49 1.00 0.15 1.20 V
VCC = 2.3 V 0.25 0.60 1.10 0.25 1.30 V
VCC = 3.0 V 0.40 0.73 1.20 0.40 1.40 V
VCC = 4.5 V 0.60 0.92 1.50 0.60 1.70 V
VCC = 5.5 V 0.70 1.02 1.70 0.70 1.90 V
NXP Semiconductors 74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
12. Dynamic characteristics
[1] Typical values are measured at Tamb =25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs.
13. Waveforms
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground=0 V). For test circuit see Figure9.
tpd propagation delay nA to nY; see Figure8 [2]
VCC= 1.65 V to 1.95V 1.0 4.2 11.0 1.0 12.0 ns
VCC= 2.3 V to 2.7V 0.5 3.0 6.5 0.5 7.2 ns
VCC= 2.7V 0.5 3.8 7.0 0.5 7.7 ns
VCC= 3.0 V to 3.6V 0.5 3.2 6.0 0.5 6.7 ns
VCC= 4.5 V to 5.5V 0.5 2.4 4.3 0.5 4.7 ns
CPD power dissipation
capacitance
VI = GND to VCC; VCC= 3.3 V [3] - 18.1 - - - pF
NXP Semiconductors 74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
14. Waveforms transfer characteristics
Table 10. Measurement points
1.65 V to 1.95V 0.5 VCC 0.5 VCC
2.3 V to 2.7V 0.5 VCC 0.5 VCC
2.7V 1.5V 1.5V
3.0V to 3.6V 1.5V 1.5V
4.5 V to 5.5V 0.5 VCC 0.5 VCC
Table 11. Test data
1.65 V to 1.95V VCC  2.0ns 30pF 1k open
2.3 V to 2.7V VCC  2.0ns 30pF 500 open
2.7V 2.7V  2.5ns 50pF 500 open
3.0V to 3.6V 2.7V  2.5ns 50pF 500 open
4.5 V to 5.5V VCC  2.5ns 50pF 500 open
NXP Semiconductors 74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
15. Application information
The slow input rise and fall times cause additional power dissipation, this can be
calculated using the following formula:
Padd =fi(tr ICC(AV) +tf ICC(AV)) VCC where:
Padd= additional power dissipation (W);= input frequency (MHz);= input rise time (ns); 10%to90%;= input fall time (ns); 90%to10 %;
ICC(AV)= average additional supply current (A).
ICC(AV) differs with positive or negative input transitions, as shown in Figure 13.
An example of a relaxation circuit using the 74LVC3G14 is shown in Figure 14.
NXP Semiconductors 74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
NXP Semiconductors 74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
16. Package outline

Partno	Mfg	Dc	Qty	Available	Descript
74LVC3G14DP	NXP	N/a	1005	avai	Triple inverting Schmitt trigger with 5 V tolerant input