74LVC3G07DC-74LVC3G07DP Fast Delivery |IC PHOENIX CO.,LIMITED

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74LVC3G07DC-74LVC3G07DP
Triple buffer with open-drain output
1. General description
The 74LVC3G07 provides three non-inverting buffers.
The output of the device is an open-drain and can be connected to other open-drain
outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.
Input can be driven from either 3.3 V or5 V devices. This feature allows the use of this
device in a mixed 3.3 V and5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall
time.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits Wide supply voltage range from 1.65 V to 5.5V5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95V) JESD8-5 (2.3 V to 2.7V) JESD8-B/JESD36 (2.7 V to 3.6 V). ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V 24 mA output drive (VCC =3.0V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C.
74L VC3G07
Triple buffer with open-drain output
Rev. 11 — 9 April 2013 Product data sheet
NXP Semiconductors 74LVC3G07
Triple buffer with open-drain output
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Table 1. Ordering information
74LVC3G07DP 40 Cto+125C TSSOP8 plastic thin shrink small outline package; 8 leads; body
width 3 mm; lead length 0.5 mm
SOT505-2
74LVC3G07DC 40 Cto+125C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74LVC3G07GT 40 Cto+125C XSON8 plastic extremely thin small outline package; no leads; 8
terminals; body 1  1.95  0.5 mm
SOT833-1
74LVC3G07GF 40 C to +125 C XSON8 extremely thin small outline package; no leads; terminals; body 1.351 0.5 mm
SOT1089
74LVC3G07GD 40 Cto+125C XSON8 plastic extremely thin small outline package; no leads; terminals; body 3  2  0.5 mm
SOT996-2
74LVC3G07GM 40 C to +125C XQFN8 plastic, extremely thin quad flat package; no leads; terminals; body 1.6 1.6 0.5 mm
SOT902-2
74LVC3G07GN 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.2 1.0 0.35 mm
SOT1116
74LVC3G07GS 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.35 1.0 0.35 mm
SOT1203
Table 2. Marking codes
74LVC3G07DP V07
74LVC3G07DC V07
74LVC3G07GT V07
74LVC3G07GF V7
74LVC3G07GD V07
74LVC3G07GM V07
74LVC3G07GN V7
74LVC3G07GS V7
NXP Semiconductors 74LVC3G07
Triple buffer with open-drain output
5. Functional diagram
6. Pinning information
6.1 Pinning
NXP Semiconductors 74LVC3G07
Triple buffer with open-drain output
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
Table 3. Pin description
1A, 2A, 3A 1, 3, 6 7, 5, 2 data input
GND 4 4 ground (0 V) , 2Y, 3Y 7, 5, 2 1, 3, 6 data output
VCC 8 8 supply voltage
Table 4. Function table[1]
NXP Semiconductors 74LVC3G07
Triple buffer with open-drain output
8. Limiting values
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC=0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI <0 V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO <0 V 50 - mA output voltage Active mode [1] 0.5 +6.5 V
Power-down mode [1][2] 0.5 +6.5 V output current VO =0V to6.5V - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40 C to +125C [3]- 250 mW
Table 6. Operating conditions
VCC supply voltage 1.65 5.5 V input voltage 0 5.5 V output voltage Active mode 0 5.5 V
Power-down mode; VCC =0V 0 5.5 V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V - 20 ns/V
VCC = 2.7 V to 5.5 V - 10 ns/V
NXP Semiconductors 74LVC3G07
Triple buffer with open-drain output
10. Static characteristicsTable 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Tamb= 40 C to +85C[1]
VIH HIGH-level input
voltage
VCC = 1.65 V to 1.95 V 0.65  VCC --V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7  VCC --V
VIL LOW-level input
voltage
VCC = 1.65 V to 1.95 V - - 0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3  VCC V
VOL LOW-level output
voltage
VI = VIH or VIL
IO = 100 A;
VCC= 1.65Vto 5.5 V 0.1 V
IO = 4 mA; VCC = 1.65 V - - 0.45 V
IO = 8 mA; VCC = 2.3 V - - 0.3 V
IO = 12 mA; VCC = 2.7 V - - 0.4 V
IO = 24 mA; VCC = 3.0 V - - 0.55 V
IO = 32 mA; VCC = 4.5 V - - 0.55 V input leakage current VI = 5.5 V or GND;
VCC =0 Vto 5.5 V
[2]- 0.1 5 A
IOZ OFF-state output
current
VI = VIH or VIL; VO = VCC or GND;
VCC = 5.5 V 0.1 10 A
IOFF power-off leakage
current
VI or VO = 5.5 V; VCC = 0 V - 0.1 10 A
ICC supply current VI = 5.5 V or GND; IO = 0 A;
VCC= 1.65Vto 5.5 V
-0.1 10 A
ICC additional supply
current
per pin; VCC = 2.3 V to 5.5 V; =VCC 0.6 V; IO =0 A
[2] -5 500 A input capacitance - 2.5 - pF
NXP Semiconductors 74LVC3G07
Triple buffer with open-drain output
[1] All typical values are measured at Tamb = 25 C.
[2] These typical values are measured at VCC =3.3V.
Tamb= 40 C to +125C
VIH HIGH-level input
voltage
VCC = 1.65 V to 1.95 V 0.65  VCC --V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7  VCC --V
VIL LOW-level input
voltage
VCC = 1.65 V to 1.95 V - - 0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3  VCC V
VOL LOW-level output
voltage
VI = VIH or VIL
IO = 100 A;
VCC= 1.65Vto 5.5V 0.1 V
IO = 4 mA; VCC = 1.65 V - - 0.70 V
IO = 8 mA; VCC = 2.3 V - - 0.45 V
IO = 12 mA; VCC = 2.7 V - - 0.60 V
IO = 24 mA; VCC = 3.0 V - - 0.80 V
IO = 32 mA; VCC = 4.5 V - - 0.80 V input leakage current VI = 5.5 V or GND;
VCC =0 Vto 5.5 V 20 A
IOZ OFF-state output
current
VI = VIH or VIL; VO = VCC or GND;
VCC = 5.5 V 10 A
IOFF power-off leakage
current
VI or VO = 5.5 V; VCC = 0 V - - 20 A
ICC supply current VI = 5.5 V or GND; IO = 0 A;
VCC= 1.65Vto 5.5 V 40 A
ICC additional supply
current
per pin; VCC = 2.3 V to 5.5 V; =VCC 0.6 V; IO =0 A 5000 A
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
NXP Semiconductors 74LVC3G07
Triple buffer with open-drain output
11. Dynamic characteristics
[1] Typical values are measured at Tamb =25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLZ and tPZL.
[3] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs.
12. Waveforms
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground=0 V). For test circuit see Figure9.
tpd propagation delay nA to nY; see Figure8 [2]
VCC= 1.65 V to 1.95V 1.0 2.9 6.7 1.0 8.4 ns
VCC= 2.3 V to 2.7V 0.5 1.7 4.3 0.5 5.5 ns
VCC= 2.7V 1.0 2.3 4.2 1.0 5.3 ns
VCC= 3.0 V to 3.6V 0.5 2.1 3.7 0.5 4.7 ns
VCC= 4.5 V to 5.5V 0.5 1.5 2.9 0.5 3.7 ns
CPD power dissipation
capacitance
VI = GND to VCC; VCC= 3.3 V [3] -6.5 - - - pF
NXP Semiconductors 74LVC3G07
Triple buffer with open-drain output
Table 9. Measurement points
1.65 V to 1.95 V 0.5  VCC 0.5  VCC VOL + 0.15 V
2.3 V to 2.7 V 0.5  VCC 0.5  VCC VOL + 0.15 V
2.7 V 1.5 V 1.5 V VOL + 0.3 V
3.0 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V
4.5 V to 5.5 V 0.5  VCC 0.5  VCC VOL + 0.3 V
Table 10. Test data
1.65 V to 1.95 V VCC  2.0 ns 30 pF 1 k 2  VCC
2.3 V to 2.7 V VCC  2.0 ns 30 pF 500  2  VCC
2.7 V 2.7 V  2.5 ns 50 pF 500  6 V
3.0 V to 3.6 V 2.7 V  2.5 ns 50 pF 500  6 V
4.5 V to 5.5 V VCC  2.5 ns 50 pF 500  2  VCC
NXP Semiconductors 74LVC3G07
Triple buffer with open-drain output
13. Package outline
NXP Semiconductors 74LVC3G07
Triple buffer with open-drain output

Partno	Mfg	Dc	Qty	Available	Descript
74LVC3G07DC	NXP	N/a	3000	avai	Triple buffer with open-drain output
74LVC3G07DP	NXP	N/a	51000	avai	Triple buffer with open-drain output