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74LVC377D-74LVC377DB-74LVC377PW
Octal D-type flip-flop with data enable; positive-edge trigger
Product specification
Supersedes data of 1996 Jun 06
IC24 Data Handbook
1998 Jul 29
Philips Semiconductors Product specification
74LVC377Octal D-type flip-flop with data enable;
positive-edge trigger
FEATURES Wide supply voltage range of 1.2V to 3.6V Conforms to JEDEC standard 8-1A Inputs accept voltages up to 5.5V CMOS low power consumption Direct interface with TTL levels Output drive capability 50Ω transmission lines @ 85°C
DESCRIPTIONThe 74LVC377 is a low-voltage Si-gate CMOS device, superior to
most advanced CMOS compatible TTL families.
The 74LVC377 has eight edge-triggered , D-type flip-flops with
individual D inputs and Q outputs. A common clock (CP) input loads
all flip-flops simultaneously when the data enable E is LOW. The
state of each D input, one set-up time before the LOW-to-HIGH
clock transition, is transferred to the corresponding output (Qn) of
the flip-flop. The E input must be stable only one set-up time prior to
the LOW-to-HIGH transition for predictable operation.
QUICK REFERENCE DATAGND = 0V; Tamb = 25°C; tr =tf 2.5 ns
NOTES:1CPD is used to determine the dynamic power dissipation (PD in μW)
PD = CPD VCC2 x fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL VCC2 fo) = sum of the outputs.
ORDERING INFORMATION
PIN CONFIGURATION
PIN DESCRIPTION
Philips Semiconductors Product specification
74LVC377Octal D-type flip-flop with data enable;
positive-edge trigger
LOGIC SYMBOL
FUNCTION TABLE= HIGH voltage level= HIGH voltage level one set-up time
prior to the LOW-to-HIGH CP transition= LOW voltage level= LOW voltage level one set-up time
prior to the LOW-to-HIGH CP transition= LOW-to-HIGH transition= Don’t care
LOGIC SYMBOL (IEEE/IEC)
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product specification
74LVC377Octal D-type flip-flop with data enable;
positive-edge trigger
ABSOLUTE MAXIMUM RATINGS1In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICSOver recommended operating conditions voltages are referenced to GND (ground = 0V)
NOTES: All typical values are at VCC = 3.3V and Tamb = 25°C.
Philips Semiconductors Product specification
74LVC377Octal D-type flip-flop with data enable;
positive-edge trigger
AC CHARACTERISTICSGND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C.
NOTE: Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25°C.
AC WAVEFORMSVM = 1.5V at VCC � 2.7V.
VM = 0.5 VCC at VCC � 2.7V.
VOL and VOH are the typical output voltage drop that occur with the output load.
Waveform 1. Clock (CP) to output (Qn) propagation delays the
clock pulse width and the maximum clock pulse frequency.
Waveform 2. Data set-up and hold times from the data input
(Dn) and from the enable
input (E) to the clock (CP).
Philips Semiconductors Product specification
74LVC377Octal D-type flip-flop with data enable;
positive-edge trigger
TEST CIRCUIT
Waveform 3. Load circuitry for switching times.
