74LVC374ABQ Fast Delivery |IC PHOENIX CO.,LIMITED

74LVC374ABQ ,74LVC374A; Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-stateapplications. A clock input (CP) and an outputs enable input (OE) are common to all flip-flops.The ..
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74LVC374ABQ
Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state
1. General description
The 74LVC374A is an octal D-type flip-flop featuring separate D-type inputs for each
flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an
outputs enable input (OE) are common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and
hold times requirements on the LOW-to-HIGH CP transition.
When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and5 V applications.
The 74LVC374A is functionally identical to the 74LVC574A, but has a different pin
arrangement.
2. Features and benefits5 V tolerant inputs/outputs; for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6V CMOS low power consumption Direct interface with TTL levels High-impedance when VCC =0V 8-bit positive edge-triggered register Independent register and 3-state buffer operation Complies with JEDEC standard: JESD8-7A (1.65Vto 1.95V) JESD8-5A (2.3Vto 2.7V) JESD8-C/JESD36 (2.7Vto 3.6V) ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-B exceeds 200V CDM JESD22-C101E exceeds 1000V Specified from 40 C to +85 C and 40 C to +125C
74L VC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs;
positive-edge trigger; 3-state
Rev. 3 — 6 December 2012 Product data sheet
NXP Semiconductors 74L VC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
74LVC374AD 40 Cto +125C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74LVC374ADB 40 Cto +125C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
74LVC374APW 40 Cto +125C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74LVC374ABQ 40 Cto +125C DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5 4.5 0.85 mm
SOT764-1
NXP Semiconductors 74L VC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
NXP Semiconductors 74L VC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description
1OE output enable input (active LOW)
Q[0:7] 2, 5, 6, 9, 12, 15, 16, 19 3-state flip-flop output
D[0:7] 3, 4, 7, 8, 13, 14, 17, 18 data input GND ground (0V) CP clock input (LOW-to-HIGH, edge-triggered) VCC supply voltage
NXP Semiconductors 74L VC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
6. Functional description
[1] H= HIGH voltage level= HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition= LOW voltage level= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition= high-impedance OFF-state= LOW-to-HIGH clock transition
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO20 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
Table 3. Function table[1]
Load and read register L  lL L  hH H
Load register and disable
outputs  lL Z  hH Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground=0V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI <0 V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO >VCC or VO <0 V - 50 mA output voltage output HIGH or LOW state [2] 0.5 VCC +0.5 V
output 3-state [2] 0.5 +6.5 V output current VO =0V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40 C to +125C [3] -500 mW
NXP Semiconductors 74L VC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
VCC supply voltage 1.65 - 3.6 V
functional 1.2 - - V input voltage 0 - 5.5 V output voltage output HIGH or LOW state 0 - VCC V
output 3-state 0 - 5.5 V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VCC =1.65V to2.7V 0 - 20 ns/V
VCC= 2.7 V to 3.6V 0 - 10 ns/V
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
VIH HIGH-level
input voltage
VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 
VCC - 0.65  VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage
VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 
VCC 0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage =VIHorVIL= 100 A;
VCC= 1.65Vto 3.6V
VCC0. VCC 0.3 - V= 4mA; VCC = 1.65 V 1.2 - - 1.05 - V= 8mA; VCC = 2.3V 1.8 - - 1.65 - V= 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V= 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V= 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage =VIHorVIL =100 A; VCC= 1.65Vto 3.6 0.2 - 0.3 V =4mA; VCC = 1.65 V - - 0.45 - 0.65 V =8mA; VCC = 2.3V - - 0.6 - 0.8 V =12mA; VCC = 2.7 V - - 0.4 - 0.6 V =24mA; VCC = 3.0 V - - 0.55 - 0.8 V
NXP Semiconductors 74L VC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
[1] All typical values are measured at VCC=3.3 V (unless stated otherwise) and Tamb =25C.
10. Dynamic characteristics input leakage
current
VCC = 3.6 V; VI =5.5 VorGND - 0.1 5- 20 A
IOZ OFF-state
output
current =VIHor VIL; VCC= 3.6 V; = 5.5Vor GND; 0.1 5- 20 A
IOFF power-off
leakage
current
VCC = 0 V; VIorVO = 5.5V - 0.1 10 - 20 A
ICC supply
current
VCC = 3.6 V; VI =VCCor GND; =0A
-0.1 10 - 40 A
ICC additional
supply
current
per input pin; VCC= 2.7Vto 3.6 V; =VCC 0.6 V; IO =0A 500 - 5000 A input
capacitance
VCC= 0 V to 3.6V; =GNDto VCC
-4.0 - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground=0 V). For test circuit see Figure 10.
tpd propagation
delayto Qn; see Figure7 [2]
VCC = 1.2 V - 16 - - - ns
VCC = 1.65 V to 1.95 V 2.2 7.4 16.3 2.2 18.8 ns
VCC = 2.3Vto 2.7V 1.5 3.9 8.4 1.5 9.7 ns
VCC = 2.7 V 1.5 3.5 8.0 1.5 10.0 ns
VCC = 3.0 V to 3.6 V 1.5 3.3 7.0 1.5 9.0 ns
ten enable time OEto Qn; see Figure8 [2]
VCC = 1.2 V - 19 - - - ns
VCC = 1.65 V to 1.95 V 1.5 6.6 16.7 1.5 19.3 ns
VCC = 2.3Vto 2.7V 1.5 3.7 9.3 1.5 10.8 ns
VCC = 2.7 V 1.5 3.8 8.5 1.5 11.0 ns
VCC = 3.0 V to 3.6 V 1.5 3.0 7.5 1.5 9.5 ns
tdis disable time OEto Qn; see Figure8 [2]
VCC = 1.2 V - 8.0 - - - ns
VCC = 1.65 V to 1.95 V 2.3 4.0 10.1 2.3 11.7 ns
VCC = 2.3Vto 2.7V 1.0 2.2 5.7 1.0 6.7 ns
VCC = 2.7 V 1.5 3.1 6.5 1.5 9.0 ns
VCC = 3.0 V to 3.6 V 1.5 2.9 6.0 1.5 7.5 ns
NXP Semiconductors 74L VC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
[1] Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where: = input frequency in MHz; fo= output frequency in MHz= output load capacitance inpF
VCC= supply voltage in Volt= number of inputs switching
(CL VCC2fo)= sum of the outputs pulse width clock HIGH or LOW; see Figure7
VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns
VCC = 2.3Vto 2.7V 4.0 - - 4.0 - ns
VCC = 2.7 V 3.0 - - 4.5 - ns
VCC = 3.0 V to 3.6 V 3.0 1.5 - 4.5 - ns
tsu set-up time Dnto CP; see Figure9
VCC = 1.65 V to 1.95 V 4.0 - - 4.0 - ns
VCC = 2.3Vto 2.7V 3.0 - - 3.0 - ns
VCC = 2.7 V 2.0 - - 2.0 - ns
VCC = 3.0 V to 3.6 V 2.0 0 - 2.0 - ns hold time Dnto CP; see Figure9
VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns
VCC = 2.3Vto 2.7V 2.0 - - 2.0 - ns
VCC = 2.7 V 1.5 - - 1.5 - ns
VCC = 3.0 V to 3.6 V 1.5 0.6 - 1.5 - ns
fmax maximum
frequency
see Figure7
VCC = 1.65 V to 1.95 V 100 - - 64 - MHz
VCC = 2.3Vto 2.7V 125 - - 100 - MHz
VCC = 2.7 V 150 - - 120 - MHz
VCC = 3.0 V to 3.6 V 150 - - 120 - MHz
tsk(o) output skew
time
VCC =3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns
CPD power
dissipation
capacitance
per flip-flop; VI = GND to VCC [4]
VCC = 1.65 V to 1.95 V - 11.6 - - - pF
VCC = 2.3 V to 2.7 V - 13.6 - - - pF
VCC = 3.0 V to 3.6 V - 15.4 - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V). For test circuit see Figure 10.
NXP Semiconductors 74L VC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
11. Waveforms
NXP Semiconductors 74L VC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
Table 8. Measurement points
1.2V VCC 0.5  VCC 0.5  VCC VOL + 0.15 V VOH  0.15 V
1.65Vto 1.95V VCC 0.5  VCC 0.5  VCC VOL + 0.15 V VOH  0.15 V
2.3Vto 2.7V VCC 0.5  VCC 0.5  VCC VOL + 0.15 V VOH  0.15 V
2.7V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V
3.0 V to 3.6V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V

Partno	Mfg	Dc	Qty	Available	Descript
74LVC374ABQ	NXP	N/a	15000	avai	74LVC374A; Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state