74LVC374A ,positive edge-trigger (3-State)Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LVC374A ,positive edge-trigger (3-State)
74LVC374ABQ ,74LVC374A; Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-stateapplications. A clock input (CP) and an outputs enable input (OE) are common to all flip-flops.The ..
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74LVC374A
OCTAL D-TYPE FLIP-FLOP HIGH PERFORMANCE
1/14July 2004 5V TOLERANT INPUTS HIGH SPEED: tPD = 6.8ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 1.65V to 3.6V (1.2V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTIONThe 74LVC374A is an advanced high-speed
CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C2 MOS technology.
These 8 bit D-Type latch are controlled by a clock
input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic state that were
setup at the D inputs.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
The Output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off. Power down protection is
provided on all inputs and 0 to 7V can be accepted
on inputs with no regard to the supply voltage.
This device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVC374AOCTAL D-TYPE FLIP-FLOP
HIGH PERFORMANCE
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes Rev. 2
74LVC374A2/14
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
Table 3: Truth Table X : Don’t Care
Z :High Impedance
74LVC374A3/14
Table 4: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
Table 5: Recommended Operating Conditions 1) Truth Table guaranteed: 1.2V to 3.6V
2) VI from 0.8V to 2V at VCC = 3.0V
74LVC374A4/14
Table 6: DC Specifications
Table 7: Dynamic Switching Characteristics 1) Number of output defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
74LVC374A5/14
Table 8: AC Electrical Characteristics 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|
2) Parameter guaranteed by design
Table 9: Capacitive Characteristics 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
74LVC374A6/14
Figure 3: Test Circuit RT = ZOUT of pulse generator (typically 50Ω)
Table 10: Test Circuit And Waveform Symbol Value
74LVC374A7/14
Figure 4: Waveform - Propagation Delay, Setup And Hold Times (f=1MHz; 50% duty cycle)
Figure 5: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle)
