74LVC2G34GM-74LVC2G34GW Fast Delivery |IC PHOENIX CO.,LIMITED

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74LVC2G34GM-74LVC2G34GW
Dual buffer gate
1. General description
The 74LVC2G34 provides two buffers.
Inputs can be driven from either 3.3Vor5 V devices. These features allow the use of
these devices in a mixed 3.3V and5 V environment.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits Wide supply voltage range from 1.65Vto 5.5V5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95V) JESD8-5 (2.3 V to 2.7V) JESD8B/JESD36 (2.7 V to 3.6V) ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V 24 mA output drive (VCC =3.0V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Multiple package options Specified from 40 Cto+85 C and 40 Cto +125 C.
74L VC2G34
Dual buffer gate
Rev. 7 — 4 July 2012 Product data sheet
NXP Semiconductors 74LVC2G34
Dual buffer gate
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
74LVC2G34GW 40 Cto +125C SC-88 plastic surface-mounted package; 6 leads SOT363
74LVC2G34GV 40 Cto +125C TSOP6 plastic surface-mounted package (TSOP6); 6 leads SOT457
74LVC2G34GM 40 Cto +125C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 1.45 0.5 mm
SOT886
74LVC2G34GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 11 0.5 mm
SOT891
74LVC2G34GN 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 0.9 1.0 0.35 mm
SOT1115
74LVC2G34GS 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 1.01.0 0.35 mm
SOT1202
Table 2. Marking
74LVC2G34GW YA
74LVC2G34GV Y34
74LVC2G34GM YA
74LVC2G34GF YA
74LVC2G34GN YA
74LVC2G34GS YA
NXP Semiconductors 74LVC2G34
Dual buffer gate
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H= HIGH voltage level; L= LOW voltage level.
Table 3. Pin description 1 data input
GND 2 ground (0V) 3 data input 4 data output
VCC 5 supply voltage 6 data output
Table 4. Function table[1]
NXP Semiconductors 74LVC2G34
Dual buffer gate
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC=0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For SC-88 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA output voltage Active mode [1][2] 0.5 VCC + 0.5 V
Power-down mode [1][2] 0.5 +6.5 V output current VO = 0 V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Ptot total power dissipation Tamb = 40 C to +125C [3]- 250 mW
Tstg storage temperature 65 +150 C
Table 6. Recommended operating conditions
VCC supply voltage 1.65 - 5.5 V input voltage 0 - 5.5 V output voltage Active mode 0 - VCC V
Power-down mode; VCC =0V 0 - 5.5 V
Tamb ambient temperature 40 - +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V - - 20 ns/V
VCC = 2.7 V to 5.5 V - - 10 ns/V
NXP Semiconductors 74LVC2G34
Dual buffer gate
10. Static characteristics
[1] All typical values are measured at VCC=3.3 V and Tamb =25C.
Table 7. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground=0V).
VIH HIGH-level
input voltage
VCC = 1.65 V to 1.95 V 0.65VCC - - 0.65VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC -V
VIL LOW-level
input voltage
VCC = 1.65 V to 1.95 V - - 0.35VCC - 0.35VCCV
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3VCC -0.3VCC V
VOH HIGH-level
output voltage =VIHorVIL= 100 A;
VCC= 1.65Vto 5.5V
VCC 0.1 - - VCC 0.1 - V= 4mA; VCC = 1.65V 1.2 - - 0.95 - V= 8mA; VCC = 2.3V 1.9 - - 1.7 - V= 12 mA; VCC = 2.7 V 2.2 - - 1.9 - V= 24 mA; VCC = 3.0 V 2.3 - - 2.0 - V= 32 mA; VCC = 4.5 V 3.8 - - 3.4 - V
VOL LOW-level
output voltage =VIHorVIL =100 A;
VCC= 1.65V to 5.5 V - 0.10 - 0.10 V =4mA; VCC = 1.65V - - 0.45 - 0.70 V =8mA; VCC = 2.3V - - 0.30 - 0.45 V =12mA; VCC = 2.7 V - - 0.40 - 0.60 V =24mA; VCC = 3.0 V - - 0.55 - 0.80 V =32mA; VCC = 4.5 V - - 0.55 - 0.80 V input leakage
current
VI = 5.5 V or GND;
VCC =0 Vto 5.5V 0.1 5- 20 A
IOFF power-off
leakage
current
VCC = 0 V; VIorVO =5.5V - 0.1 10 - 20 A
ICC supply current VI = 5.5 V or GND; IO = 0 A;
VCC= 1.65Vto 5.5 V
-0.1 10 - 40 A
ICC additional
supply current
per pin; VCC = 2.3 V to 5.5 V; =VCC 0.6 V; IO =0 A 5 500 - 5000 A input
capacitance
VCC =3.3 V; VI = GND to VCC -2.5 - - - pF
NXP Semiconductors 74LVC2G34
Dual buffer gate
11. Dynamic characteristics
[1] Typical values are measured at Tamb =25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs.
12. Waveforms
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground=0 V); for load circuit see Figure8.
tpd propagation delay nA to nY; see Figure7 [2]
VCC= 1.65 V to 1.95V 1.0 3.8 8.6 1.0 10.8 ns
VCC= 2.3 V to 2.7V 0.5 2.4 4.4 0.5 5.5 ns
VCC= 2.7V 0.5 2.5 5.0 0.5 6.3 ns
VCC= 3.0 V to 3.6V 0.5 2.2 4.1 0.5 5.1 ns
VCC= 4.5 V to 5.5V 0.5 1.9 3.2 0.5 4.0 ns
CPD power dissipation
capacitance
VI = GND to VCC; VCC= 3.3 V [3] -20- - - pF
NXP Semiconductors 74LVC2G34
Dual buffer gate
Table 9. Measurement points
1.65 V to 1.95V 0.5VCC 0.5VCC
2.3 V to 2.7V 0.5VCC 0.5VCC
2.7V 1.5V 1.5V
3.0V to 3.6V 1.5V 1.5V
4.5 V to 5.5V 0.5VCC 0.5VCC
Table 10. Test data
1.65 V to 1.95V VCC  2.0ns 30pF 1k open
2.3 V to 2.7V VCC  2.0ns 30pF 500 open
2.7V 2.7V  2.5ns 50pF 500 open
3.0V to 3.6V 2.7V  2.5ns 50pF 500 open
4.5 V to 5.5V VCC  2.5ns 50pF 500 open
NXP Semiconductors 74LVC2G34
Dual buffer gate
13. Package outline
NXP Semiconductors 74LVC2G34
Dual buffer gate

Partno	Mfg	Dc	Qty	Available	Descript
74LVC2G34GM	NXP/PHILIPS	N/a	5000	avai	Dual buffer gate
74LVC2G34GM	NXP	N/a	20000	avai	Dual buffer gate
74LVC2G34GW	NXP	N/a	3042	avai	Dual buffer gate