74LVC2G32DP-74LVC2G32GT Fast Delivery |IC PHOENIX CO.,LIMITED

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74LVC2G32DP-74LVC2G32GT
Dual 2-input OR gate
1. General description
The 74LVC2G32 provides a 2-input OR gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features and benefits Wide supply voltage range from 1.65 Vto 5.5V5 V tolerant outputs in the Power-down mode High noise immunity 24 mA output drive (VCC =3.0V) CMOS low power consumption Complies with JEDEC standard: JESD8-7 (1.65 Vto 1.95V) JESD8-5 (2.3 Vto 2.7V) JESD8-B/JESD36 (2.7 Vto 3.6V) Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5V ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Multiple package options Specified from 40 Cto +85 C and 40 Cto+125C
74L VC2G32
Dual 2-input OR gate
Rev. 11 — 8 April 2013 Product data sheet
NXP Semiconductors 74LVC2G32
Dual 2-input OR gate
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Table 1. Ordering information
74LVC2G32DP 40 C to +125C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74LVC2G32DC 40 C to +125C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74LVC2G32GT 40 C to +125C XSON8 plastic extremely thin small outline package; no leads; terminals; body 1 1.95 0.5 mm
SOT833-1
74LVC2G32GF 40 C to +125 C XSON8 extremely thin small outline package; no leads; terminals; body 1.351 0.5 mm
SOT1089
74LVC2G32GD 40Cto +125C XSON8 plastic extremely thin small outline package; no leads; terminals; body 3  2  0.5 mm
SOT996-2
74LVC2G32GM 40 C to +125C XQFN8 plastic, extremely thin quad flat package; no leads; terminals; body 1.6 1.6 0.5 mm
SOT902-2
74LVC2G32GN 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.2 1.0 0.35 mm
SOT1116
74LVC2G32GS 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.35 1.0 0.35 mm
SOT1203
Table 2. Marking codes
74LVC2G32DP V32
74LVC2G32DC V32
74LVC2G32GT V32
74LVC2G32GF VG
74LVC2G32GD V32
74LVC2G32GM V32
74LVC2G32GN VG
74LVC2G32GS VG
NXP Semiconductors 74LVC2G32
Dual 2-input OR gate
5. Functional diagram
6. Pinning information
6.1 Pinning
NXP Semiconductors 74LVC2G32
Dual 2-input OR gate
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level.
Table 3. Pin description
1A, 2A 1, 5 7, 3 data input
1B, 2B 2, 6 6, 2 data input
GND 4 4 ground (0V), 2Y 7, 3 1, 5 data output
VCC 8 8 supply voltage
Table 4. Function table[1]
LLL H H
HHH
NXP Semiconductors 74LVC2G32
Dual 2-input OR gate
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC=0 V (Power-down mode), the output voltage can be 5.5 V in normal condition.
[3] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground=0V).
VCC supply voltage 0.5 +6.5 V input voltage [1] 0.5 +6.5 V output voltage Active mode [1] 0.5 VCC + 0.5 V
Power-down mode [2] 0.5 +6.5 V
IIK input clamping current VI <0V 50 - mA
IOK output clamping current VO <0V or VO >VCC - 50 mA output current VO =0VtoVCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40 C to +125C [3]- 300 mW
Table 6. Operating conditions
VCC supply voltage 1.65 5.5 V input voltage 0 5.5 V output voltage Active mode 0 VCC V
Power-down mode 0 5.5 V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCC =1.65V to2.7V - 20 ns/V
VCC= 2.7 V to 5.5V - 10 ns/V
NXP Semiconductors 74LVC2G32
Dual 2-input OR gate
10. Static characteristicsTable 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
Tamb= 40 C to +85C[1]
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65  VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7  VCC -- V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3  VCC V
VOH HIGH-level output voltage VI =VIH or VIL= 100 A; VCC= 1.65 V to 5.5V VCC  0.1 - - V= 4 mA; VCC =1.65V 1.2 1.53 - V= 8 mA; VCC= 2.3V 1.9 2.13 - V= 12 mA; VCC= 2.7V 2.2 2.50 - V= 24 mA; VCC= 3.0V 2.3 2.60 - V= 32 mA; VCC= 4.5V 3.8 4.10 - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V
IO = 4 mA; VCC = 1.65 V - 0.08 0.45 V
IO = 8 mA; VCC = 2.3 V - 0.14 0.3 V
IO = 12 mA; VCC = 2.7 V - 0.19 0.4 V
IO = 24 mA; VCC = 3.0 V - 0.37 0.55 V
IO = 32 mA; VCC = 4.5 V - 0.43 0.55 V input leakage current VI= 5.5Vor GND; VCC =0Vto 5.5V - 0.1 5 A
IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - 0.1 10 A
ICC supply current VI= 5.5Vor GND;
VCC= 1.65Vto 5.5V; IO =0A
-0.1 10 A
ICC additional supply current per pin; VI = VCC  0.6 V; IO = 0A;
VCC= 2.3 V to 5.5 V 500 A input capacitance - 2.5 - pF
Tamb= 40 C to +125C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65  VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7  VCC -- V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3  VCC V
NXP Semiconductors 74LVC2G32
Dual 2-input OR gate
[1] All typical values are measured at Tamb = 25C.
11. Dynamic characteristics
VOH HIGH-level output voltage VI =VIH or VIL= 100 A; VCC= 1.65 V to 5.5V VCC  0.1 - - V= 4 mA; VCC= 1.65V 0.95 - - V= 8 mA; VCC= 2.3V 1.7 - - V= 12 mA; VCC= 2.7V 1.9 - - V= 24 mA; VCC= 3.0V 2.0 - - V= 32 mA; VCC= 4.5V 3.4 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V
IO = 4 mA; VCC = 1.65 V - - 0.70 V
IO = 8 mA; VCC = 2.3 V - - 0.45 V
IO = 12 mA; VCC = 2.7 V - - 0.60 V
IO = 24 mA; VCC = 3.0 V - - 0.80 V
IO = 32 mA; VCC = 4.5 V - - 0.80 V input leakage current VI= 5.5Vor GND; VCC =0Vto 5.5V - - 20 A
IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - 20 A
ICC supply current VI= 5.5Vor GND;
VCC= 1.65Vto 5.5V; IO =0A 40 A
ICC additional supply current per pin; VI = VCC  0.6 V; IO = 0A;
VCC= 2.3 V to 5.5 V 5000 A
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground 0 V); for test circuit see Figure9.
tpd propagation delay nA, nB to nY; see Figure8 [2]
VCC= 1.65Vto 1.95V 1.3 3.9 8.8 1.3 11 ns
VCC= 2.3Vto 2.7V 0.8 2.4 4.7 0.8 5.9 ns
VCC= 2.7V 0.8 2.7 4.8 0.8 6.0 ns
VCC= 3.0Vto 3.6V 0.9 2.2 4.2 0.9 5.3 ns
VCC= 4.5Vto 5.5V 0.7 1.7 3.2 0.7 4.0 ns
NXP Semiconductors 74LVC2G32
Dual 2-input OR gate
[1] Typical values are measured at nominal VCC and at Tamb= 25 C.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC 2  fi  N + (CL  VCC 2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC 2  fo) = sum of outputs.
12. Waveforms
CPD power dissipation
capacitance
per gate; VI = GND to VCC [3] -14 - - - pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground 0 V); for test circuit see Figure9.
Table 9. Measurement points
1.65 V to 1.95 V 0.5VCC 0.5VCC
2.3 V to 2.7 V 0.5VCC 0.5VCC
2.7 V 1.5 V 1.5 V
3.0 V to 3.6 V 1.5 V 1.5 V
4.5 V to 5.5 V 0.5VCC 0.5VCC
NXP Semiconductors 74LVC2G32
Dual 2-input OR gate
Table 10. Test data
1.65 V to 1.95 V VCC  2.0 ns 30 pF 1 k open
2.3 V to 2.7 V VCC  2.0 ns 30 pF 500  open
2.7 V 2.7 V  2.5 ns 50 pF 500  open
3.0 V to 3.6 V 2.7 V  2.5 ns 50 pF 500  open
4.5 V to 5.5 V VCC  2.5 ns 50 pF 500  open
NXP Semiconductors 74LVC2G32
Dual 2-input OR gate
13. Package outline
NXP Semiconductors 74LVC2G32
Dual 2-input OR gate

Partno	Mfg	Dc	Qty	Available	Descript
74LVC2G32DP	NXP	N/a	853	avai	Dual 2-input OR gate
74LVC2G32GT	NXP	N/a	750	avai	Dual 2-input OR gate