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74LVC2G126DC-74LVC2G126DP-74LVC2G126GT
Dual bus buffer/line driver; 3-state
1. General descriptionThe 74LVC2G126 is a dual non-inverting buffer/line driver with 3-state outputs. Each
3-state output is controlled by an output enable input (pin nOE). A LOW-level at pin nOE
causes the output to assume a high-impedance OFF-state. Schmitt trigger action at all
inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3Vor5 V devices. This feature allows the use of the
74LVC2G126 as a translator in a mixed 3.3V and5 V environment.
It is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing a damaging backflow current through the device when it is
powered down.
2. Features and benefits Wide supply voltage range from 1.65Vto 5.5V5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (VCC =3.0V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5V Multiple package options Specified from 40 Cto+85 C and 40 Cto +125 C
74L VC2G126
Dual bus buffer/line driver; 3-state
Rev. 12 — 8 April 2013 Product data sheet
NXP Semiconductors 74LVC2G126
Dual bus buffer/line driver; 3-state
3. Ordering information
4. Marking[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Table 1. Ordering information74LVC2G126DP 40 Cto +125C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74LVC2G126DC 40 Cto +125C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74LVC2G126GT 40 Cto +125C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 1 1.95 0.5 mm
SOT833-1
74LVC2G126GF 40 C to +125 C XSON8 extremely thin small outline package; no leads; terminals; body 1.351 0.5 mm
SOT1089
74LVC2G126GD 40 Cto +125C XSON8 plastic extremely thin small outline package; no leads; terminals; body 3 2 0.5 mm
SOT996-2
74LVC2G126GM 40 C to +125C XQFN8 plastic, extremely thin quad flat package; no leads; terminals; body 1.6 1.6 0.5 mm
SOT902-2
74LVC2G126GN 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.21.0 0.35 mm
SOT1116
74LVC2G126GS 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.35 1.0 0.35 mm
SOT1203
Table 2. Marking codes74LVC2G126DP V26
74LVC2G126DC V26
74LVC2G126GT V26
74LVC2G126GF VN
74LVC2G126GD V26
74LVC2G126GM V26
74LVC2G126GN VN
74LVC2G126GS VN
NXP Semiconductors 74LVC2G126
Dual bus buffer/line driver; 3-state
5. Functional diagram
6. Pinning information
6.1 PinningNXP Semiconductors 74LVC2G126
Dual bus buffer/line driver; 3-state
6.2 Pin description
7. Functional description[1] H= HIGH voltage level; L= LOW voltage level; X= don’t care; Z= high-impedance OFF-state.
Table 3. Pin description1OE, 2OE 1, 7 7, 1 output enable input (active HIGH)
1A, 2A 2, 5 6, 3 data input, 2Y 6, 3 2, 5 data output
GND 4 4 ground (0V)
VCC 8 8 supply voltage
Table 4. Function table[1] L
HHH Z
NXP Semiconductors 74LVC2G126
Dual bus buffer/line driver; 3-state
8. Limiting values[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP8 packages: above 55 C the value of Ptot derates linearly at 2.5 mW/K.
For VSSOP8 packages: above 110 C the value of Ptot derates linearly at 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 5. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA output voltage Active mode [1] 0.5 VCC + 0.5 V
Power-down mode [1][2] 0.5 +6.5 V output current VO = 0 V to VCC - 50 mA
ICC supply current - +100 mA
IGND ground current 100 - mA
Ptot total power dissipation Tamb = 40 C to +125C [3]- 300 mW
Tstg storage temperature 65 +150 C
Table 6. Operating conditionsVCC supply voltage 1.65 5.5 V input voltage 0 5.5 V output voltage Active mode 0 VCC V
VCC = 0 V; Power-down mode 0 5.5 V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V - 20 ns/V
VCC = 2.7 V to 5.5 V - 10 ns/V
NXP Semiconductors 74LVC2G126
Dual bus buffer/line driver; 3-state
10. Static characteristicsTable 7. Static characteristicsAt recommended operating conditions; voltages are referenced to GND (ground = 0V).
Tamb= 40 Cto+85C
VIH HIGH-level input voltage VCC= 1.65Vto 1.95V 0.65 VCC -- V
VCC= 2.3Vto 2.7V 1.7 - - V
VCC= 2.7Vto 3.6V 2.0 - - V
VCC= 4.5Vto 5.5V 0.7 VCC -- V
VIL LOW-level input voltage VCC= 1.65Vto 1.95V - - 0.35 VCC V
VCC= 2.3Vto 2.7V - - 0.7 V
VCC= 2.7Vto 3.6V - - 0.8 V
VCC= 4.5Vto 5.5V - - 0.3 VCC V
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 A; VCC =1.65Vto 5.5V - - 0.1 V
IO = 4 mA; VCC= 1.65V - - 0.45 V
IO = 8 mA; VCC =2.3V - - 0.3 V
IO = 12 mA; VCC= 2.7V - - 0.4 V
IO = 24 mA; VCC= 3.0V - - 0.55 V
IO = 32 mA; VCC= 4.5V - - 0.55 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 100 A; VCC= 1.65Vto 5.5V VCC 0.1 - - V
IO = 4 mA; VCC =1.65V 1.2 - - V
IO = 8 mA; VCC =2.3V 1.9 - - V
IO = 12 mA; VCC =2.7V 2.2 - - V
IO = 24 mA; VCC =3.0V 2.3 - - V
IO = 32 mA; VCC =4.5V 3.8 - - V input leakage current VI= 5.5Vor GND; VCC =0Vto 5.5V - 0.1 5 A
IOZ OFF-state output current VI = VIH or VIL; VO= 5.5Vor GND;
VCC= 3.6 V 0.1 10 A
IOFF power-off leakage current VI or VO =5.5 V; VCC =0 V - 0.1 10 A
ICC supply current VI= 5.5Vor GND;
VCC= 1.65Vto 5.5V; IO =0A
-0.1 10 A
ICC additional supply current per pin; VI =VCC 0.6 V; IO =0A;
VCC = 2.3 V to 5.5 V 500 A input capacitance - 2 - pF
NXP Semiconductors 74LVC2G126
Dual bus buffer/line driver; 3-state[1] Typical values are measured at VCC = 3.3 V and Tamb= 25 C.
Tamb= 40C
to +125 C VIH HIGH-level input voltage VCC= 1.65Vto 1.95V 0.65 VCC -- V
VCC= 2.3Vto 2.7V 1.7 - - V
VCC= 2.7Vto 3.6V 2.0 - - V
VCC= 4.5Vto 5.5V 0.7 VCC -- V
VIL LOW-level input voltage VCC= 1.65Vto 1.95V - - 0.35 VCC V
VCC= 2.3Vto 2.7V - - 0.7 V
VCC= 2.7Vto 3.6V - - 0.8 V
VCC= 4.5Vto 5.5V - - 0.3 VCC V
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 A; VCC =1.65Vto 5.5V - - 0.1 V
IO = 4 mA; VCC= 1.65V - - 0.70 V
IO = 8 mA; VCC =2.3V - - 0.45 V
IO = 12 mA; VCC= 2.7V - - 0.60 V
IO = 24 mA; VCC= 3.0V - - 0.80 V
IO = 32 mA; VCC= 4.5V - - 0.80 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 100 A; VCC= 1.65Vto 5.5V VCC 0.1 - - V
IO = 4 mA; VCC= 1.65V 0.95 - - V
IO = 8 mA; VCC =2.3V 1.7 - - V
IO = 12 mA; VCC =2.7V 1.9 - - V
IO = 24 mA; VCC =3.0V 2.0 - - V
IO = 32 mA; VCC =4.5V 3.4 - - V input leakage current VI= 5.5Vor GND; VCC =0Vto 5.5V - - 20 A
IOZ OFF-state output current VI = VIH or VIL; VO= 5.5Vor GND;
VCC= 3.6 V 20 A
IOFF power-off leakage current VI or VO =5.5 V; VCC =0 V - - 20 A
ICC supply current VI= 5.5Vor GND;
VCC= 1.65Vto 5.5V; IO =0A 40 A
ICC additional supply current per pin; VI =VCC 0.6 V; IO =0A;
VCC = 2.3 V to 5.5 V 5 mA
Table 7. Static characteristics …continuedAt recommended operating conditions; voltages are referenced to GND (ground = 0V).
NXP Semiconductors 74LVC2G126
Dual bus buffer/line driver; 3-state
11. Dynamic characteristics[1] Typical values are measured at Tamb =25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL
[3] ten is the same as tPZH and tPZL
[4] tdis is the same as tPLZ and tPHZ
[5] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs.
Table 8. Dynamic characteristicsVoltages are referenced to GND (ground = 0 V); for test circuit see Figure9.
tpd propagation delay nA to nY; see Figure7 [2]
VCC= 1.65Vto 1.95V 1.0 3.9 9.8 1.0 12.3 ns
VCC= 2.3Vto 2.7V 0.5 2.6 4.9 0.5 6.3 ns
VCC= 2.7V 1.0 2.8 4.7 1.0 5.9 ns
VCC= 3.0Vto 3.6V 0.5 2.4 4.3 0.5 5.4 ns
VCC= 4.5Vto 5.5V 0.5 1.9 3.2 0.5 4.0 ns
ten enable time nOE to nY; see Figure8 [3]
VCC= 1.65Vto 1.95V 1.0 4.1 10.0 1.0 12.5 ns
VCC= 2.3Vto 2.7V 1.0 2.6 5.0 1.0 6.3 ns
VCC= 2.7V 1.0 2.8 4.7 1.0 5.9 ns
VCC= 3.0Vto 3.6V 1.0 2.4 4.1 1.0 5.1 ns
VCC= 4.5Vto 5.5V 0.5 1.8 3.1 0.5 3.9 ns
tdis disable time nOE to nY; see Figure8 [4]
VCC= 1.65Vto 1.95V 1.0 3.3 12.6 1.0 15.4 ns
VCC= 2.3Vto 2.7V 0.5 1.9 5.7 0.5 7.5 ns
VCC= 2.7V 1.5 3.0 4.8 1.5 6.2 ns
VCC= 3.0Vto 3.6V 1.0 2.5 4.4 1.0 5.7 ns
VCC= 4.5Vto 5.5V 0.5 1.8 3.3 0.5 4.4 ns
CPD power dissipation
capacitance
per buffer; VI = GND to VCC [5]
output enabled - 17 - - - pF
output disabled - 5 - - - pF
NXP Semiconductors 74LVC2G126
Dual bus buffer/line driver; 3-state
12. Waveforms
Table 9. Measurement points1.65Vto 1.95V 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
2.3Vto 2.7V 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
2.7V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V
3.0Vto 3.6V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V
4.5Vto 5.5V 0.5 VCC 0.5 VCC VOL + 0.3 V VOH 0.3 V
NXP Semiconductors 74LVC2G126
Dual bus buffer/line driver; 3-state
Table 10. Test data1.65 V to 1.95V VCC 2.0ns 30pF 1k open GND 2 VCC
2.3 V to 2.7V VCC 2.0ns 30pF 500 open GND 2 VCC
2.7V 2.7 V 2.5ns 50pF 500 open GND 6 V
3.0 V to 3.6V 2.7 V 2.5ns 50pF 500 open GND 6 V
4.5 V to 5.5V VCC 2.5ns 50pF 500 open GND 2 VCC
NXP Semiconductors 74LVC2G126
Dual bus buffer/line driver; 3-state
13. Package outline