74LVC2G125DC-74LVC2G125GD-74LVC2G125GT Fast Delivery |IC PHOENIX CO.,LIMITED

74LVC2G125GD ,Dual bus buffer/line driver; 3-state 74LVC2G125Dual bus buffer/line driver; 3-stateRev. 14 — 29 March 2013 Product data sheet1.
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74LVC2G125DC-74LVC2G125GD-74LVC2G125GT
Dual bus buffer/line driver; 3-state
1. General description
The 74LVC2G125 provides a dual non-inverting buffer/line driver with 3-state output.
The 3-state output is controlled by the output enable input (pin nOE). A HIGH-level at pin
nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at
all inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (VCC = 3.0 V) CMOS low-power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C
74L VC2G125
Dual bus buffer/line driver; 3-state
Rev. 14 — 29 March 2013 Product data sheet
NXP Semiconductors 74LVC2G125
Dual bus buffer/line driver; 3-state
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Table 1. Ordering information
74LVC2G125DP 40 Cto+125C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74LVC2G125DC 40 Cto+125C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74LVC2G125GT 40 Cto+125C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 1  1.95  0.5 mm
SOT833-1
74LVC2G125GF 40 C to +125 C XSON8 extremely thin small outline package; no leads; terminals; body 1.351 0.5 mm
SOT1089
74LVC2G125GD 40 Cto+125C XSON8 plastic extremely thin small outline package; no leads; terminals; body 3  2  0.5 mm
SOT996-2
74LVC2G125GM 40 C to +125C XQFN8 plastic, extremely thin quad flat package; no leads; terminals; body 1.6 1.6 0.5 mm
SOT902-2
74LVC2G125GN 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.2 1.0 0.35 mm
SOT1116
74LVC2G125GS 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.35 1.0 0.35 mm
SOT1203
Table 2. Marking codes
74LVC2G125DP V25
74LVC2G125DC V25
74LVC2G125GT V25
74LVC2G125GF VM
74LVC2G125GD V25
74LVC2G125GM V25
74LVC2G125GN VM
74LVC2G125GS VM
NXP Semiconductors 74LVC2G125
Dual bus buffer/line driver; 3-state
5. Functional diagram
6. Pinning information
6.1 Pinning
NXP Semiconductors 74LVC2G125
Dual bus buffer/line driver; 3-state
6.2 Pin description
7. Functional description
[1] H= HIGH voltage level; L= LOW voltage level; X= don’t care; Z= high-impedance OFF-state.
Table 3. Pin description
1OE, 2OE 1, 7 7, 1 output enable input (active LOW)
1A, 2A 2, 5 6, 3 data input
GND 4 4 ground (0 V), 2Y 6, 3 2, 5 data output
VCC 8 8 supply voltage
Table 4. Function table[1]
LLL H Z
NXP Semiconductors 74LVC2G125
Dual bus buffer/line driver; 3-state
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8, XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground 0V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO <0 V - 50 mA output voltage Enable mode [1] 0.5 VCC + 0.5 V
Disable mode [1] 0.5 +6.5 V
Power-down mode [1][2] 0.5 +6.5 V output current VO = 0 V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40Cto +125C [3] -300 mW
Table 6. Operating conditions
VCC supply voltage 1.65 5.5 V input voltage 0 5.5 V output voltage VCC = 1.65 V to 5.5 V; Enable mode 0 VCC V
VCC = 1.65 V to 5.5 V; Disable mode 0 5.5 V
VCC = 0 V; Power-down mode 0 5.5 V
Tamb ambient temperature 40 +125 C
t/V input transition rise and
fall rate
VCC = 1.65 V to 2.7 V - 20 ns/V
VCC = 2.7 V to 5.5 V - 10 ns/V
NXP Semiconductors 74LVC2G125
Dual bus buffer/line driver; 3-state
10. Static characteristicsTable 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0V).
Tamb= 40 Cto+85C
VIH HIGH-level input voltage VCC= 1.65Vto 1.95V 0.65VCC -- V
VCC= 2.3Vto 2.7V 1.7 - - V
VCC= 2.7Vto 3.6V 2.0 - - V
VCC= 4.5Vto 5.5V 0.7VCC -- V
VIL LOW-level input voltage VCC= 1.65Vto 1.95V - - 0.35VCC V
VCC= 2.3Vto 2.7V - - 0.7 V
VCC= 2.7Vto 3.6V - - 0.8 V
VCC= 4.5Vto 5.5V - - 0.3VCC V
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 A; VCC =1.65Vto 5.5V - - 0.1 V
IO = 4 mA; VCC =1.65V - - 0.45 V
IO = 8 mA; VCC= 2.3V - - 0.3 V
IO = 12 mA; VCC =2.7V - - 0.4 V
IO = 24 mA; VCC =3.0V - - 0.55 V
IO = 32 mA; VCC =4.5V - - 0.55 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 100 A; VCC= 1.65Vto 5.5V VCC  0.1 - - V
IO = 4 mA; VCC =1.65V 1.2 - - V
IO = 8 mA; VCC =2.3V 1.9 - - V
IO = 12 mA; VCC= 2.7V 2.2 - - V
IO = 24 mA; VCC= 3.0V 2.3 - - V
IO = 32 mA; VCC= 4.5V 3.8 - - V input leakage current VI= 5.5Vor GND; VCC =0Vto 5.5V - 0.1 5 A
IOZ OFF-state output current VI = VIH or VIL; VO= 5.5Vor GND;
VCC= 3.6 V 0.1 10 A
IOFF power-off leakage current VI or VO =5.5 V; VCC =0 V - 0.1 10 A
ICC supply current VI= 5.5Vor GND;
VCC= 1.65Vto 5.5V; IO =0A
-0.1 10 A
ICC additional supply current per pin; VI =VCC 0.6 V; IO =0A;
VCC = 2.3 V to 5.5 V 500 A input capacitance - 2 - pF
NXP Semiconductors 74LVC2G125
Dual bus buffer/line driver; 3-state
[1] Typical values are measured at VCC = 3.3 V and Tamb= 25 C.
Tamb= 40Cto +125 C
VIH HIGH-level input voltage VCC= 1.65Vto 1.95V 0.65VCC -- V
VCC= 2.3Vto 2.7V 1.7 - - V
VCC= 2.7Vto 3.6V 2.0 - - V
VCC= 4.5Vto 5.5V 0.7VCC -- V
VIL LOW-level input voltage VCC= 1.65Vto 1.95V - - 0.35VCC V
VCC= 2.3Vto 2.7V - - 0.7 V
VCC= 2.7Vto 3.6V - - 0.8 V
VCC= 4.5Vto 5.5V - - 0.3VCC V
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 A; VCC =1.65Vto 5.5V - - 0.1 V
IO = 4 mA; VCC =1.65V - - 0.70 V
IO = 8 mA; VCC= 2.3V - - 0.45 V
IO = 12 mA; VCC =2.7V - - 0.60 V
IO = 24 mA; VCC =3.0V - - 0.80 V
IO = 32 mA; VCC =4.5V - - 0.80 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 100 A; VCC= 1.65Vto 5.5V VCC  0.1 - - V
IO = 4 mA; VCC= 1.65V 0.95 - - V
IO = 8 mA; VCC =2.3V 1.7 - - V
IO = 12 mA; VCC= 2.7V 1.9 - - V
IO = 24 mA; VCC= 3.0V 2.0 - - V
IO = 32 mA; VCC= 4.5V 3.4 - - V input leakage current VI= 5.5Vor GND; VCC =0Vto 5.5V - - 20 A
IOZ OFF-state output current VI = VIH or VIL; VO= 5.5Vor GND;
VCC= 3.6 V 20 A
IOFF power-off leakage current VI or VO =5.5 V; VCC =0 V - - 20 A
ICC supply current VI= 5.5Vor GND;
VCC= 1.65Vto 5.5V; IO =0A 40 A
ICC additional supply current per pin; VI =VCC 0.6 V; IO =0A;
VCC = 2.3 V to 5.5 V 5 mA
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground 0V).
NXP Semiconductors 74LVC2G125
Dual bus buffer/line driver; 3-state
11. Dynamic characteristics
[1] Typical values are measured at nominal VCC and at Tamb= 25 C.
[2] tpd is the same as tPLH and tPHL.
[3] ten is the same as tPZH and tPZL.
[4] tdis is the same as tPLZ and tPHZ.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC 2  fi  N + (CL  VCC 2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC 2  fo) = sum of outputs.
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground 0 V); for test circuit see Figure9.
tpd propagation delay nA to nY; see Figure7 [2]
VCC= 1.65Vto 1.95V 1.0 3.7 9.1 1.0 11.4 ns
VCC= 2.3Vto 2.7V 0.5 2.5 4.8 0.5 6.0 ns
VCC= 2.7V 1.0 2.7 4.8 1.0 6.0 ns
VCC= 3.0Vto 3.6V 0.5 2.3 4.3 0.5 5.5 ns
VCC= 4.5Vto 5.5V 0.5 1.9 3.7 0.5 4.6 ns
ten enable time nOEto nY; see Figure8 [3]
VCC= 1.65Vto 1.95V 1.5 4.3 9.9 1.5 12.4 ns
VCC= 2.3Vto 2.7V 1.0 2.8 5.6 1.0 7.0 ns
VCC= 2.7V 1.5 3.3 5.7 1.5 7.1 ns
VCC= 3.0Vto 3.6V 0.5 2.4 4.7 0.5 5.9 ns
VCC= 4.5Vto 5.5V 0.5 2.0 3.8 0.5 4.8 ns
tdis disable time nOEto nY; see Figure8 [4]
VCC= 1.65Vto 1.95V 1.0 3.5 11.6 1.0 14.1 ns
VCC= 2.3Vto 2.7V 0.5 1.8 5.8 0.5 7.6 ns
VCC= 2.7V 1.0 2.7 4.8 1.0 6.2 ns
VCC= 3.0Vto 3.6V 1.0 2.7 4.6 1.0 5.9 ns
VCC= 4.5Vto 5.5V 0.5 1.8 3.4 0.5 4.6 ns
CPD power dissipation
capacitance
per buffer; VI = GND to VCC [5]
output enabled - 18 - - - pF
output disabled - 5 - - - pF
NXP Semiconductors 74LVC2G125
Dual bus buffer/line driver; 3-state
12. Waveforms
Table 9. Measurement points
1.65Vto 1.95V 0.5VCC 0.5VCC VOL + 0.15 V VOH  0.15 V
2.3Vto 2.7V 0.5VCC 0.5VCC VOL + 0.15 V VOH  0.15 V
2.7V 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V
3.0Vto 3.6V 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V
4.5Vto 5.5V 0.5VCC 0.5VCC VOL + 0.3 V VOH  0.3 V
NXP Semiconductors 74LVC2G125
Dual bus buffer/line driver; 3-state
Table 10. Test data
1.65 V to 1.95V VCC  2.0ns 30pF 1k open GND 2VCC
2.3 V to 2.7V VCC  2.0ns 30pF 500 open GND 2VCC
2.7V 2.7 V  2.5ns 50pF 500 open GND 6 V
3.0 V to 3.6V 2.7 V  2.5ns 50pF 500 open GND 6 V
4.5 V to 5.5V VCC  2.5ns 50pF 500 open GND 2VCC
NXP Semiconductors 74LVC2G125
Dual bus buffer/line driver; 3-state
13. Package outline

Partno	Mfg	Dc	Qty	Available	Descript
74LVC2G125DC	NXP	N/a	100	avai	Dual bus buffer/line driver; 3-state
74LVC2G125GD	NXP	N/a	13700	avai	Dual bus buffer/line driver; 3-state
74LVC2G125GT	PHI	N/a	5000	avai	Dual bus buffer/line driver; 3-state