74LVC1G74DC-74LVC1G74GM-74LVC1G74GT Fast Delivery |IC PHOENIX CO.,LIMITED

74LVC1G74GM ,74LVC1G74; Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74Single D-type flip-flop with set and reset; positive edge triggerRev. 12 — 2 April 2013 P ..
74LVC1G74GM ,74LVC1G74; Single D-type flip-flop with set and reset; positive edge triggerFEATURES DESCRIPTION• Wide supply voltage range from 1.65 V to 5.5 V The 74LVC1G74 is a high-perfor ..
74LVC1G74GT ,Single D-type flip-flop with set and reset; positive edge triggerFeatures and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for inte ..
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74LVC1G74DC-74LVC1G74GM-74LVC1G74GT
Single D-type flip-flop with set and reset; positive edge trigger
1. General description
The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D)
inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q andQ
outputs.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing damaging backflow current through the device
when it is powered down.
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time
prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
2. Features and benefits Wide supply voltage range from 1.65 Vto 5.5V5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 Vto 1.95V) JESD8-5 (2.3 Vto 2.7V) JESD8-B/JESD36 (2.7 Vto 3.6V) ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V 24 mA output drive (VCC =3.0V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from 40 Cto+85 C and 40 Cto+125C
74L VC1G74
Single D-type flip-flop with set and reset; positive edge trigger
Rev. 12 — 2 April 2013 Product data sheet
NXP Semiconductors 74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Table 1. Ordering information
74LVC1G74DP 40 Cto +125C TSSOP8 plastic thin shrink small outline package; 8 leads; body
width 3 mm; lead length 0.5 mm
SOT505-2
74LVC1G74DC 40 Cto +125C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74LVC1G74GT 40 Cto +125C XSON8 plastic extremely thin small outline package; no leads; 8
terminals; body 1  1.95  0.5 mm
SOT833-1
74LVC1G74GF 40 C to +125 C XSON8 extremely thin small outline package; no leads; terminals; body 1.351 0.5 mm
SOT1089
74LVC1G74GD 40 Cto +125C XSON8 plastic extremely thin small outline package; no leads; terminals; body 3  2  0.5 mm
SOT996-2
74LVC1G74GM 40 Cto +125C XQFN8 plastic, extremely thin quad flat package; no leads; terminals; body 1.6  1.6  0.5 mm
SOT902-2
74LVC1G74GN 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.2 1.0 0.35 mm
SOT1116
74LVC1G74GS 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.35 1.0 0.35 mm
SOT1203
Table 2. Marking codes
74LVC1G74DP V74
74LVC1G74DC V74
74LVC1G74GT V74
74LVC1G74GF Y4
74LVC1G74GD V74
74LVC1G74GM V74
74LVC1G74GN Y4
74LVC1G74GS Y4
NXP Semiconductors 74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
5. Functional diagram
NXP Semiconductors 74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
6. Pinning information
6.1 Pinning
NXP Semiconductors 74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
6.2 Pin description
7. Functional description
[1] H= HIGH voltage level;= LOW voltage level;= don’t care.
[1] H= HIGH voltage level;= LOW voltage level;= LOW-to-HIGH CP transition;
Qn+1= state after the next LOW-to-HIGH CP transition.
Table 3. Pin description 1 7 clock input (LOW-to-HIGH, edge-triggered) 2 6 data input 3 5 complement output
GND 4 4 ground (0V) 5 3 true output 6 2 asynchronous reset-direct input (active LOW) 7 1 asynchronous set-direct input (active LOW)
VCC 8 8 supply voltage
Table 4. Function table for asynchronous operation[1] H XXH L L XXL H L XXH H
Table 5. Function table for synchronous operation[1]  LLH  HHL
NXP Semiconductors 74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC=0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP8 packages: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI <0V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO >VCC or VO <0V - 50 mA output voltage Active mode [1] 0.5 VCC +0.5 V
Power-down mode [1][2] 0.5 +6.5 V output current VO =0 VtoVCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Ptot total power dissipation Tamb = 40 C to +125C [3]- 300 mW
Tstg storage temperature 65 +150 C
Table 7. Operating conditions
VCC supply voltage 1.65 5.5 V input voltage 0 5.5 V output voltage Active mode 0 VCC V
Power-down mode; VCC =0V 0 5.5 V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCC= 1.65 V to 2.7V - 20 ns/V
VCC= 2.7 V to 5.5V - 10 ns/V
NXP Semiconductors 74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
10. Static characteristicsTable 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb = 40 C to +85C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65  VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7  VCC -- V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3  VCC V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V VCC  0.1 - - V
IO = 4 mA; VCC = 1.65 V 1.2 1.54 - V
IO = 8 mA; VCC = 2.3 V 1.9 2.15 - V
IO = 12 mA; VCC = 2.7 V 2.2 2.50 - V
IO = 24 mA; VCC = 3.0 V 2.3 2.62 - V
IO = 32 mA; VCC = 4.5 V 3.8 4.11 - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.10 V
IO = 4 mA; VCC = 1.65 V - 0.07 0.45 V
IO = 8 mA; VCC = 2.3 V - 0.12 0.30 V
IO = 12 mA; VCC = 2.7 V - 0.17 0.40 V
IO = 24 mA; VCC = 3.0 V - 0.33 0.55 V
IO = 32 mA; VCC = 4.5 V - 0.39 0.55 V input leakage current VI= 5.5Vor GND;
VCC =0 Vto 5.5V 0.1 5 A
IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - 0.1 10 A
ICC supply current VI= 5.5Vor GND;
VCC= 1.65Vto 5.5V; IO =0A
-0.1 10 A
ICC additional supply current per pin; VI = VCC  0.6 V; IO = 0A;
VCC =2.3 V to 5.5 V 500 A input capacitance - 4.0 - pF
NXP Semiconductors 74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
[1] All typical values are measured at Tamb = 25 C.
Tamb = 40 C to +125C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65  VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7  VCC -- V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3  VCC V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V VCC  0.1 - - V
IO = 4 mA; VCC = 1.65 V 0.95 - - V
IO = 8 mA; VCC = 2.3 V 1.7 - - V
IO = 12 mA; VCC = 2.7 V 1.9 - - V
IO = 24 mA; VCC = 3.0 V 2.0 - - V
IO = 32 mA; VCC = 4.5 V 3.4 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.10 V
IO = 4 mA; VCC = 1.65 V - - 0.70 V
IO = 8 mA; VCC = 2.3 V - - 0.45 V
IO = 12 mA; VCC = 2.7 V - - 0.60 V
IO = 24 mA; VCC = 3.0 V - - 0.80 V
IO = 32 mA; VCC = 4.5 V - - 0.80 V input leakage current VI= 5.5Vor GND;
VCC =0 Vto 5.5V 20 A
IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - 20 A
ICC supply current VI= 5.5Vor GND;
VCC= 1.65Vto 5.5V; IO =0A 40 A
ICC additional supply current per pin; VI = VCC  0.6 V; IO = 0A;
VCC =2.3 V to 5.5 V 5000 A
Table 8. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
11. Dynamic characteristicsTable 9. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
tpd propagation delay CP to Q, Q; see Figure8 [2]
VCC = 1.65 V to 1.95 V 1.5 6.0 13.4 1.5 13.4 ns
VCC = 2.3 V to 2.7 V 1.0 3.5 7.1 1.0 7.1 ns
VCC = 2.7 V 1.0 3.5 7.1 1.0 7.1 ns
VCC = 3.0 V to 3.6 V 1.0 3.5 5.9 1.0 5.9 ns
VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 1.0 4.1 ns
SD to Q, Q; see Figure9 [2]
VCC = 1.65 V to 1.95 V 1.5 6.0 12.9 1.5 12.9 ns
VCC = 2.3 V to 2.7 V 1.0 3.5 7.0 1.0 7.0 ns
VCC = 2.7 V 1.0 3.5 7.0 1.0 7.0 ns
VCC = 3.0 V to 3.6 V 1.0 3.0 5.9 1.0 5.9 ns
VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 1.0 4.1 ns
RD to Q, Q; see Figure9 [2]
VCC = 1.65 V to 1.95 V 1.5 5.0 12.9 1.5 12.9 ns
VCC = 2.3 V to 2.7 V 1.0 3.5 7.0 1.0 7.0 ns
VCC = 2.7 V 1.0 3.5 7.0 1.0 7.0 ns
VCC = 3.0 V to 3.6 V 1.0 3.0 5.9 1.0 5.9 ns
VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 1.0 4.1 ns pulse width CP HIGH or LOW;
see Figure8
VCC = 1.65 V to 1.95 V 6.2 - - 6.2 - ns
VCC = 2.3 V to 2.7 V 2.7 - - 2.7 - ns
VCC = 2.7 V 2.7 - - 2.7 - ns
VCC = 3.0 V to 3.6 V 2.7 1.3 - 2.7 - ns
VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - ns
SD and RDLOW;
see Figure9
VCC = 1.65 V to 1.95 V 6.2 - - 6.2 - ns
VCC = 2.3 V to 2.7 V 2.7 - - 2.7 - ns
VCC = 2.7 V 2.7 - - 2.7 - ns
VCC = 3.0 V to 3.6 V 2.7 1.6 - 2.7 - ns
VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - ns
NXP Semiconductors 74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
[1] Typical values are measured at Tamb =25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs.
trec recovery time SD or RD; see Figure9
VCC = 1.65 V to 1.95 V 1.9 - - 1.9 - ns
VCC = 2.3 V to 2.7 V 1.4 - - 1.4 - ns
VCC = 2.7 V 1.3 - - 1.3 - ns
VCC = 3.0 V to 3.6 V +1.2 3.0 - +1.2 - ns
VCC = 4.5 V to 5.5 V 1.0 - - 1.0 - ns
tsu set-up time Dto CP; see Figure8
VCC = 1.65 V to 1.95 V 2.9 - - 2.9 - ns
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - ns
VCC = 2.7 V 1.7 - - 1.7 - ns
VCC = 3.0 V to 3.6 V 1.3 0.5 - 1.3 - ns
VCC = 4.5 V to 5.5 V 1.1 - - 1.1 - ns hold time Dto CP; see Figure8
VCC = 1.65 V to 1.95 V 1.5 - - 1.5 - ns
VCC = 2.3 V to 2.7 V 1.0 - - 1.0 - ns
VCC = 2.7 V 1.0 - - 1.0 - ns
VCC = 3.0 V to 3.6 V 1.0 0.6 - 1.0 - ns
VCC = 4.5 V to 5.5 V 1.0 - - 1.0 - ns
fmax maximum
frequency
CP; see Figure8
VCC = 1.65 V to 1.95 V 80 - - 80 - MHz
VCC = 2.3 V to 2.7 V 175 - - 175 - MHz
VCC = 2.7 V 175 - - 175 - MHz
VCC = 3.0 V to 3.6 V 175 280 - 175 - MHz
VCC = 4.5 V to 5.5 V 200 - - 200 - MHz
CPD power dissipation
capacitance
VI = GND to VCC;
VCC =3.3V
[3] -15- - - pF
Table 9. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
NXP Semiconductors 74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
12. Waveforms
Table 10. Measurement points
1.65 V to 1.95V 0.5 VCC 0.5 VCC
2.3 V to 2.7V 0.5 VCC 0.5 VCC 1.5V 1.5V 1.5V 1.5V V to 5.5V 0.5 VCC 0.5 VCC
NXP Semiconductors 74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
NXP Semiconductors 74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
Table 11. Test data
1.65 V to 1.95V VCC  2.0ns 30pF 1k open GND 2VCC
2.3 V to 2.7V VCC  2.0ns 30pF 500 open GND 2VCC
2.7V 2.7 V  2.5ns 50pF 500 open GND 6 V
3.0 V to 3.6V 2.7 V  2.5ns 50pF 500 open GND 6 V
4.5 V to 5.5V VCC  2.5ns 50pF 500 open GND 2VCC

Partno	Mfg	Dc	Qty	Available	Descript
74LVC1G74DC	NXP	N/a	1	avai	Single D-type flip-flop with set and reset; positive edge trigger
74LVC1G74GM	NXP	N/a	10151	avai	74LVC1G74; Single D-type flip-flop with set and reset; positive edge trigger
74LVC1G74GT	NXP	N/a	9915	avai	Single D-type flip-flop with set and reset; positive edge trigger