74LVC1G38GM-74LVC1G38GW Fast Delivery |IC PHOENIX CO.,LIMITED

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74LVC1G38GM-74LVC1G38GW
2-input NAND gate; open drain
1. General description
The 74LVC1G38 provides a 2-input NAND function.
Inputs can be driven from either 3.3 Vor5 V devices. This feature allows the use of this
device as translator in a mixed 3.3 V and5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits Wide supply voltage range from 1.65Vto 5.5V5 V tolerant outputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7(1.65 Vto1.95V) JESD8-5 (2.3 Vto 2.7V) JESD8-B/JESD36 (2.7 Vto 3.6 V). ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V 24 mA output drive (VCC =3.0V) CMOS low power consumption Open drain outputs Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5V Multiple package options Specified from 40 Cto +125 C.
74L VC1G38
2-input NAND gate; open drain
Rev. 7 — 4 October 2012 Product data sheet
NXP Semiconductors 74LVC1G38
2-input NAND gate; open drain
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
74LVC1G38GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
74LVC1G38GV 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753
74LVC1G38GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1  1.45  0.5 mm
SOT886
74LVC1G38GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 11 0.5 mm
SOT891
74LVC1G38GN 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 0.9 1.0 0.35 mm
SOT1115
74LVC1G38GS 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 1.0 1.0 0.35 mm
SOT1202
74LVC1G38GX 40 C to +125C X2SON5 X2SON5: plastic thermal enhanced extremely thin
small outline package; no leads; 5 terminals;
body 0.8 0.8 0.35 mm
SOT1226
Table 2. Marking
74LVC1G38GW YB
74LVC1G38GV YB
74LVC1G38GM YB
74LVC1G38GF YB
74LVC1G38GN YB
74LVC1G38GS YB
74LVC1G38GX YB
NXP Semiconductors 74LVC1G38
2-input NAND gate; open drain
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 3. Pin description 1 1 data input 2 2 data input
GND 3 3 ground (0V) 4 4 data output
n.c. - 5 not connected
VCC 5 6 supply voltage
NXP Semiconductors 74LVC1G38
2-input NAND gate; open drain
7. Functional description
[1] H= HIGH voltage level; L= LOW voltage level; Z= high-impedance OFF state
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC=0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 and X2SON 5packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
Table 4. Function table[1]
LLZ Z Z
HHL
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI <0V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO >VCC or VO <0V - 50 mA output voltage Active mode [1][2] 0.5 +6.5 V
Power-down mode [1][2] 0.5 +6.5 V output current VO =0VtoVCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40 C to +125C [3]- 300 mW
NXP Semiconductors 74LVC1G38
2-input NAND gate; open drain
9. Recommended operating conditions
10. Static characteristics
Table 6. Recommended operating conditions
VCC supply voltage 1.65 - 5.5 V input voltage 0 - 5.5 V output voltage Active mode 0 - 5.5 V
Disable mode; VCC= 1.65Vto 5.5V 0 - 5.5 V
Power-down mode; VCC= 0 V 0 - 5.5 V
Tamb ambient temperature 40 - +125 C
t/V input transition rise and
fall rate
VCC = 1.65 V to 2.7 V - - 20 ns/V
VCC = 2.7 V to 5.5 V - - 10 ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb= 40 C to +85C[1]
VIH HIGH-level input voltage VCC = 1.65 Vto 1.95 V 0.65 VCC -- V
VCC = 2.3 Vto 2.7 V 1.7 - - V
VCC = 2.7 Vto 3.6 V 2.0 - - V
VCC = 4.5 Vto 5.5 V 0.7  VCC -- V
VIL LOW-level input voltage VCC = 1.65 Vto 1.95 V - - 0.35 VCCV
VCC = 2.3 Vto 2.7 V - - 0.7 V
VCC = 2.7 Vto 3.6 V - - 0.8 V
VCC = 4.5 Vto 5.5 V - - 0.3  VCC V
VOL LOW-level output voltage VI =VIHorVIL -- - =100 A; VCC= 1.65Vto 5.5 V - - 0.1 V =4mA; VCC = 1.65V - - 0.45 V =8mA; VCC = 2.3V - - 0.3 V =12mA; VCC = 2.7V - - 0.4 V =24mA; VCC = 3.0V - - 0.55 V =32mA; VCC = 4.5V - - 0.55 V input leakage current VI= 5.5Vor GND;
VCC =0 Vto 5.5V 0.1 5 A
IOZ OFF-state output current VI =VIHor VIL; VO =VCCor GND;
VCC = 5.5 V 0.1 10 A
IOFF power-off leakage current VIorVO =5.5 V; VCC = 0V - 0.1 10 A
ICC supply current VI= 5.5Vor GND;
VCC= 1.65Vto 5.5V; IO =0A
-0.1 10 A
ICC additional supply current VI =VCC 0.6 V; IO =0A;
VCC= 2.3Vto 5.5 V; per pin 500 A input capacitance - 2.5 - pF
NXP Semiconductors 74LVC1G38
2-input NAND gate; open drain
[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 C.
Tamb= 40 C to +125C
VIH HIGH-level input voltage VCC = 1.65 Vto 1.95 V 0.65 VCC -- V
VCC = 2.3 Vto 2.7 V 1.7 - - V
VCC = 2.7 Vto 3.6 V 2.0 - - V
VCC = 4.5 Vto 5.5 V 0.7  VCC -- V
VIL LOW-level input voltage VCC = 1.65 Vto 1.95 V - - 0.35 VCCV
VCC = 2.3 Vto 2.7 V - - 0.7 V
VCC = 2.7 Vto 3.6 V - - 0.8 V
VCC = 4.5 Vto 5.5 V - - 0.3  VCC V
VOL LOW-level output voltage VI =VIHorVIL -- - =100 A; VCC= 1.65Vto 5.5 V - - 0.1 V =4mA; VCC = 1.65V - - 0.70 V =8mA; VCC = 2.3V - - 0.45 V =12mA; VCC = 2.7V - - 0.60 V =24mA; VCC = 3.0V - - 0.80 V =32mA; VCC = 4.5V - - 0.80 V input leakage current VI= 5.5Vor GND;
VCC =0 Vto 5.5V 100 A
IOZ OFF-state output current VI =VIHor VIL; VO =VCCor GND;
VCC = 5.5 V 200 A
IOFF power-off leakage current VIorVO =5.5 V; VCC = 0V - - 200 A
ICC supply current VI= 5.5Vor GND;
VCC= 1.65Vto 5.5V; IO =0A 200 A
ICC additional supply current VI =VCC 0.6 V; IO =0A;
VCC= 2.3Vto 5.5 V; per pin 5000 A
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74LVC1G38
2-input NAND gate; open drain
11. Dynamic characteristics
[1] Typical values are measured at Tamb =25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPZL and tPLZ.
[3] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs.
12. AC waveforms
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground=0 V). For test circuit see Figure9.
tpd propagation delay A, Bto Y; see Figure8 [2]
VCC = 1.65 V to 1.95 V 1.0 3.0 10.0 1.0 12.5 ns
VCC = 2.3 V to 2.7 V 0.5 1.8 6.0 0.5 7.5 ns
VCC = 2.7 V 0.5 2.5 5.0 0.5 6.5 ns
VCC = 3.0 V to 3.6 V 0.5 2.3 4.5 0.5 5.7 ns
VCC = 4.5 V to 5.5 V 0.5 1.5 3.9 0.5 4.9 ns
CPD power dissipation
capacitance
VCC =3.3V; =GNDto VCC
[3] -6- - - pF
NXP Semiconductors 74LVC1G38
2-input NAND gate; open drain
Table 9. Measurement points
1.65 Vto 1.95V 0.5 VCC 0.5 VCC VOL +0.15V
2.3 Vto 2.7V 0.5 VCC 0.5 VCC VOL +0.15V
2.7V 1.5V 1.5V VOL +0.3V
3.0 Vto 3.6V 1.5V 1.5V VOL +0.3V
4.5 Vto 5.5V 0.5 VCC 0.5 VCC VOL +0.3V
Table 10. Test data
1.65 V to 1.95V VCC  2.0ns 30pF 1k open
2.3 V to 2.7V VCC  2.0ns 30pF 500 open
2.7V 2.7V  2.5ns 50pF 500 open
3.0 V to 3.6V 2.7V  2.5ns 50pF 500 open
4.5 V to 5.5V VCC  2.5ns 50pF 500 open
NXP Semiconductors 74LVC1G38
2-input NAND gate; open drain
13. Package outline
NXP Semiconductors 74LVC1G38
2-input NAND gate; open drain

Partno	Mfg	Dc	Qty	Available	Descript
74LVC1G38GM	NXP/PHILIPS	N/a	5000	avai	2-input NAND gate; open drain
74LVC1G38GW	NXP	N/a	65	avai	74LVC1G38; 2-input NAND gate (open drain)