74LVC1G175GM-74LVC1G175GW Fast Delivery |IC PHOENIX CO.,LIMITED

74LVC1G175GM ,Single D-type flip-flop with reset; positive-edge triggerFeatures and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for inte ..
74LVC1G175GW ,Single D-type flip-flop with reset; positive-edge triggerapplications using I . The I OFF OFFcircuitry disables the output, preventing the damaging backflow ..
74LVC1G175GW ,Single D-type flip-flop with reset; positive-edge triggerFeatures■ Wide supply voltage range from 1.65 V to 5.5 V■ 5 V tolerant inputs for interfacing with ..
74LVC1G175GW ,Single D-type flip-flop with reset; positive-edge triggerGeneral descriptionThe 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type ..
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74LVC1G175GM-74LVC1G175GW
Single D-type flip-flop with reset; positive edge trigger
1. General description
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type
flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q
output.
The master reset (MR) is an asynchronous active LOW input and operates independently
of the clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time
prior to the LOW-to-HIGH clock transition for predictable operation.
The inputs can be driven from either 3.3 Vor5 V devices. This feature allows the use of
this device in a mixed 3.3 V and5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
2. Features and benefits Wide supply voltage range from 1.65 Vto 5.5V5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 Vto 1.95V) JESD8-5 (2.3 Vto 2.7V) JESD8B/JESD36 (2.7 Vto 3.6 V). ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V. 24 mA output drive (VCC =3.0V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5V Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C.
74L VC1G175
Single D-type flip-flop with reset; positive-edge trigger
Rev. 6 — 11 October 2013 Product data sheet
NXP Semiconductors 74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
74LVC1G175GW 40Cto +125C SC-88 plastic surface-mounted package; 6 leads SOT363
74LVC1G175GV 40Cto +125C SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457
74LVC1G175GM 40Cto +125C XSON6 plastic extremely thin small outline package; leads; 6 terminals; body 1 1.45 0.5 mm
SOT886
74LVC1G175GF 40 C to +125 C XSON6 plastic extremely thin small outline package; leads; 6 terminals; body 11 0.5 mm
SOT891
74LVC1G175GN 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 0.9 1.0 0.35 mm
SOT1115
74LVC1G175GS 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 1.0 1.0 0.35 mm
SOT1202
Table 2. Marking
74LVC1G175GW YT
74LVC1G175GV V75
74LVC1G175GM YT
74LVC1G175GF YT
74LVC1G175GN YT
74LVC1G175GS YT
NXP Semiconductors 74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 3. Pin description 1 clock input (LOW-to-HIGH, edge-triggered)
GND 2 ground (0V) 3 data input 4 output Q
VCC 5 supply voltage 6 master reset input (active LOW)
NXP Semiconductors 74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
7. Functional description
[1] H= HIGH voltage level;= HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;= LOW voltage level;= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;= LOW-to-HIGH CP transition;= don’t care.
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC=0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For SC-88 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
Table 4. Function table[1]
Reset (clear) L X X L
Load ‘1’ H  hH
Load ‘0’ H  lL
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA output voltage Active mode [1][2] 0.5 VCC + 0.5 V
Power-down mode [1][2] 0.5 +6.5 V output current VO = 0 V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Ptot total power dissipation Tamb = 40 C to +125C [3]- 250 mW
Tstg storage temperature 65 +150 C
NXP Semiconductors 74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
9. Recommended operating conditions
10. Static characteristics
Table 6. Recommended operating conditions
VCC supply voltage 1.65 - 5.5 V input voltage 0 - 5.5 V output voltage Active mode 0 - VCC V
Power-down mode; VCC =0V 0 - 5.5 V
Tamb ambient temperature 40 - +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V - - 20 ns/V
VCC = 2.7 V to 5.5 V - - 10 ns/V
Table 7. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground=0V).
Tamb= 40 C to +85C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7 VCC -- V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 VCC V
VOH HIGH-level output voltage VI =VIHorVIL= 100 A; VCC = 1.65 V to 5.5V VCC 0.1 - - V= 4mA; VCC = 1.65V 1.2 1.54 - V= 8mA; VCC = 2.3V 1.9 2.15 - V= 12 mA; VCC = 2.7 V 2.2 2.50 - V= 24 mA; VCC = 3.0 V 2.3 2.62 - V= 32 mA; VCC = 4.5 V 3.8 4.11 - V
VOL LOW-level output voltage VI =VIHorVIL =100 A; VCC = 1.65 V to 5.5 V - - 0.10 V =4mA; VCC = 1.65V - 0.07 0.45 V =8mA; VCC = 2.3V - 0.12 0.30 V =12mA; VCC = 2.7 V - 0.17 0.40 V =24mA; VCC = 3.0 V - 0.33 0.55 V =32mA; VCC = 4.5 V - 0.39 0.55 V input leakage current VCC = 0 V to 5.5 V; VI =5.5V orGND [2]- 0.1 5 A
IOFF power-off leakage current VCC = 0 V; VIorVO =5.5V - 0.1 10 A
NXP Semiconductors 74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
[1] All typical values are measured at Tamb = 25 C.
[2] These typical values are measured at VCC =3.3V.
ICC supply current VCC = 1.65 V to 5.5 V; IO =0A; = 5.5 Vor GND
-0.1 10 A
ICC additional supply current VCC = 2.3 V to 5.5 V; VI =VCC 0.6V; =0 A
[2] -5 500 A input capacitance VCC= 3.3 V; VI = GND to VCC -2.5 - pF
Tamb= 40 C to +125C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7 VCC -- V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 VCC V
VOH HIGH-level output voltage VI =VIHorVIL= 100 A; VCC = 1.65 V to 5.5V VCC 0.1 - - V= 4mA; VCC = 1.65V 0.95 - - V= 8mA; VCC = 2.3V 1.7 - - V= 12 mA; VCC = 2.7 V 1.9 - - V= 24 mA; VCC = 3.0 V 2.0 - - V= 32 mA; VCC = 4.5 V 3.4 - - V
VOL LOW-level output voltage VI =VIHorVIL =100 A; VCC = 1.65 V to 5.5 V - - 0.10 V =4mA; VCC = 1.65V - - 0.70 V =8mA; VCC = 2.3V - - 0.45 V =12mA; VCC = 2.7 V - - 0.60 V =24mA; VCC = 3.0 V - - 0.80 V =32mA; VCC = 4.5 V - - 0.80 V input leakage current VCC = 0 V to 5.5 V; VI =5.5V orGND - - 20 A
IOFF power-off leakage current VCC = 0 V; VIorVO =5.5V - - 20 A
ICC supply current VCC = 1.65 V to 5.5 V; IO =0A; = 5.5 Vor GND 40 A
ICC additional supply current VCC = 2.3 V to 5.5 V; VI =VCC 0.6V; =0 A - 5000 A
Table 7. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground=0V).
NXP Semiconductors 74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
11. Dynamic characteristicsTable 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure9.
tpd propagation delay CP to Q; see Figure7 [2]
VCC = 1.65 V to 1.95 V 1.5 4.9 13.4 1.5 17 ns
VCC = 2.3 V to 2.7 V 1.0 3.1 7.1 1.0 9.0 ns
VCC = 2.7 V 1.0 3.2 7.1 1.0 9.0 ns
VCC = 3.0 V to 3.6 V 1.0 3.1 5.7 0.5 7.5 ns
VCC = 4.5 V to 5.5 V 1.0 2.2 4.0 0.5 5.5 ns
MR to Q; see Figure8
VCC = 1.65 V to 1.95 V 1.5 4.3 12.9 1.5 17 ns
VCC = 2.3 V to 2.7 V 1.0 2.8 7.0 1.0 9.0 ns
VCC = 2.7 V 1.0 3.0 7.0 1.0 9.0 ns
VCC = 3.0 V to 3.6 V 1.0 2.5 5.8 0.5 7.5 ns
VCC = 4.5 V to 5.5 V 1.0 2.0 4.1 0.5 5.5 ns pulse width CP HIGH or LOW;
see Figure7
VCC = 1.65 V to 1.95 V 6.2 - - 6.2 - ns
VCC = 2.3 V to 2.7 V 2.7 - - 2.7 - ns
VCC = 2.7 V 2.7 - - 2.7 - ns
VCC = 3.0 V to 3.6 V 2.7 1.3 - 2.7 - ns
VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - ns
MR LOW; see Figure8
VCC = 1.65 V to 1.95 V 6.2 - - 6.2 - ns
VCC = 2.3 V to 2.7 V 2.7 - - 2.7 - ns
VCC = 2.7 V 2.7 - - 2.7 - ns
VCC = 3.0 V to 3.6 V 2.7 1.6 - 2.7 - ns
VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - ns
trec recovery time MR; see Figure8
VCC = 1.65 V to 1.95 V 1.9 - - 1.9 - ns
VCC = 2.3 V to 2.7 V 1.4 - - 1.4 - ns
VCC = 2.7 V 1.3 - - 1.3 - ns
VCC = 3.0 V to 3.6 V 1.2 0.4 - 1.2 - ns
VCC = 4.5 V to 5.5 V 1.0 - - 1.0 - ns
tsu set-up time D to CP; see Figure7
VCC = 1.65 V to 1.95 V 2.9 - - 2.9 - ns
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - ns
VCC = 2.7 V 1.7 - - 1.7 - ns
VCC = 3.0 V to 3.6 V 1.3 0.5 - 1.3 - ns
VCC = 4.5 V to 5.5 V 1.1 - - 1.1 - ns
NXP Semiconductors 74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
[1] Typical values are measured at Tamb =25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in Volts;= number of inputs switching;
(CL VCC2fo)= sum of the outputs. hold time D to CP; see Figure7
VCC = 1.65 V to 1.95 V 0.0 - - 0.0 - ns
VCC = 2.3 V to 2.7 V 0.3 - - 0.3 - ns
VCC = 2.7 V 0.5 - - 0.5 - ns
VCC = 3.0 V to 3.6 V 1.2 0.2 - 1.2 - ns
VCC = 4.5 V to 5.5 V 0.5 - - 0.5 - ns
fmax maximum
frequency
CP; see Figure7
VCC = 1.65 V to 1.95 V 80 125 - 80 - MHz
VCC = 2.3 V to 2.7 V 175 - - 175 - MHz
VCC = 2.7 V 175 - - 175 - MHz
VCC = 3.0 V to 3.6 V 175 300 - 175 - MHz
VCC = 4.5 V to 5.5 V 200 - - 200 - MHz
CPD power dissipation
capacitance
VI = GND to VCC; VCC =3.3V [3] -14 - - - pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure9.
NXP Semiconductors 74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
12. Waveforms
NXP Semiconductors 74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Table 9. Measurement points
1.65 V to 1.95V 0.5 VCC 0.5 VCC
2.3 V to 2.7V 0.5 VCC 0.5 VCC
2.7V 1.5V 1.5V
3.0V to 3.6V 1.5V 1.5V
4.5 V to 5.5V 0.5 VCC 0.5 VCC
Table 10. Test data
1.65 V to 1.95V VCC  2.0ns 30pF 1k open
2.3 V to 2.7V VCC  2.0ns 30pF 500 open
2.7V 2.7V  2.5ns 50pF 500 open
3.0V to 3.6V 2.7V  2.5ns 50pF 500 open
4.5 V to 5.5V VCC  2.5ns 50pF 500 open

Partno	Mfg	Dc	Qty	Available	Descript
74LVC1G175GM	NXP	N/a	275000	avai	Single D-type flip-flop with reset; positive-edge trigger
74LVC1G175GW	NXP/PHIL	N/a	9000	avai	Single D-type flip-flop with reset; positive-edge trigger
74LVC1G175GW	NXP	N/a	3000	avai	Single D-type flip-flop with reset; positive-edge trigger