74LVC1G00GF-74LVC1G00GM-74LVC1G00GW Fast Delivery |IC PHOENIX CO.,LIMITED

74LVC1G00GW ,Single 2-input NAND gatePin configuration SOT886 74LVC1G0074LVC1G00B 1 5 VCCB 1 6 VCC3GNDA 2 5 n.c.A 2 4 YGND 3 4 Y001aaf05 ..
74LVC1G02 ,SINGLE 2 INPUT POSITIVE NOR GATE
74LVC1G02GM ,Single 2-input NOR gateFeatures and benefits Wide supply voltage range from 1.65 V to 5.5 V High noise immunity Complie ..
74LVC1G02GV ,Single 2-input NOR gateLogic diagram74LVC1G02 All information provided in this document is subject to legal disclaimers. ..
74LVC1G02GW ,Single 2-input NOR gateINTEGRATED CIRCUITSDATA SHEET74LVC1G02Single 2-input NOR gateProduct speciﬁcation 2004 Sep 07Supers ..
74LVC1G02SE-7 , SINGLE 2 INPUT POSITIVE NOR GATE
80CNQ035A ,35V 80A Schottky Common Cathode Diode in a D61-8 packageapplications are in switching power supplies, convert-waveformers, free-wheeling diodes, and revers ..
80CNQ040 ,40V 80A Schottky Common Cathode Diode in a D61-8 packageFeaturesThe 80CNQ center tap Schottky rectifier module series hasbeen optimized for very low forwar ..
80CNQ040ASL ,40V 80A Schottky Common Cathode Diode in a D61-8-SL packageFeaturesMajor Ratings and CharacteristicsThe 80CNQ...A center tap Schottky rectifier module series ..
80CNQ045 ,45V 80A Schottky Common Cathode Diode in a D61-8 packagePD-2.216 rev. C 01/9980CNQ... SERIESSCHOTTKY RECTIFIER 80 AmpMajor Ratings and Characteristics De ..
80CNQ045A ,45V 80A Schottky Common Cathode Diode in a D61-8 packageBulletin PD-20038 rev. A 09/0180CNQ...A SERIES80 AmpSCHOTTKY RECTIFIERNew GenIII D-61 Package ..
80CNQ045A ,45V 80A Schottky Common Cathode Diode in a D61-8 packageapplications are in switching power supplies, convert-waveformers, free-wheeling diodes, and revers ..

74LVC1G00GF-74LVC1G00GM-74LVC1G00GW
Single 2-input NAND-gate
1. General description
The 74LVC1G00 provides the single 2-input NAND function.
Input can be driven from either 3.3Vor5 V devices. These features allow the use of
these devices in a mixed 3.3V and5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall
time.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits Wide supply voltage range from 1.65Vto 5.5V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65Vto 1.95V) JESD8-5 (2.3Vto 2.7V) JESD8-B/JESD36 (2.7Vto 3.6V) 24 mA output drive (VCC =3.0V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5V Multiple package options ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Specified from 40 Cto+85 C and 40 Cto +125 C
74L VC1G00
Single 2-input NAND gate
Rev. 10 — 2 July 2012 Product data sheet
NXP Semiconductors 74LVC1G00
Single 2-input NAND gate
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
74LVC1G00GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; leads; body width 1.25 mm
SOT353-1
74LVC1G00GV 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753
74LVC1G00GM 40 C to +125 C XSON6 plastic extremely thin small outline package; leads; 6 terminals; body 1  1.45  0.5 mm
SOT886
74LVC1G00GF 40 C to +125 C XSON6 plastic extremely thin small outline package; leads; 6 terminals; body 11 0.5 mm
SOT891
74LVC1G00GN 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 0.9 1.0 0.35 mm
SOT1115
74LVC1G00GS 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 1.0 1.0 0.35 mm
SOT1202
74LVC1G00GX 40 C to +125C X2SON5 X2SON5: plastic thermal enhanced extremely
thin small outline package; no leads; 5
terminals; body 0.8 0.8 0.35 mm
SOT1226
Table 2. Marking codes
74LVC1G00GW VA
74LVC1G00GV V00
74LVC1G00GM VA
74LVC1G00GF VA
74LVC1G00GN VA
74LVC1G00GS VA
74LVC1G00GX VA
NXP Semiconductors 74LVC1G00
Single 2-input NAND gate
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 3. Pin description 1 1 data input 2 2 data input
GND 3 3 ground (0 V) 4 4 data output
n.c. - 5 not connected
VCC 5 6 supply voltage
NXP Semiconductors 74LVC1G00
Single 2-input NAND gate
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC=0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 and X2SON5 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
Table 4. Function table[1]
LLH H H
HHL
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA output voltage Active mode [1][2] 0.5 VCC + 0.5 V
Power-down mode [1][2] 0.5 +6.5 V output current VO = 0 V to VCC - 50 mA
ICC supply current - +100 mA
IGND ground current 100 - mA
Ptot total power dissipation Tamb = 40 C to +125C [3]- 250 mW
Tstg storage temperature 65 +150 C
NXP Semiconductors 74LVC1G00
Single 2-input NAND gate
9. Recommended operating conditions
10. Static characteristics
Table 6. Recommended operating conditions
VCC supply voltage 1.65 - 5.5 V input voltage 0 - 5.5 V output voltage Active mode 0 - VCC V
VCC = 0 V; Power-down mode 0 - 5.5 V
Tamb ambient temperature 40 - +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V - - 20 ns/V
VCC = 2.7 V to 5.5 V - - 10 ns/V
Table 7. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground=0V).
VIH HIGH-level
input voltage
VCC = 1.65 V to 1.95 V 0.65VCC - - 0.65VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC -V
VIL LOW-level
input voltage
VCC = 1.65 V to 1.95 V - - 0.35VCC -0.35VCCV
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3VCC -0.3VCC V
VOH HIGH-level
output voltage =VIHorVIL= 100 A;
VCC= 1.65V to 5.5V
VCC 0.1 - - VCC 0.1 - V= 4mA; VCC = 1.65V 1.2 - - 0.95 - V= 8mA; VCC = 2.3V 1.9 - - 1.7 - V= 12 mA; VCC = 2.7 V 2.2 - - 1.9 - V= 24 mA; VCC = 3.0 V 2.3 - - 2.0 - V= 32 mA; VCC = 4.5 V 3.8 - - 3.4 - V
VOL LOW-level
output voltage =VIHorVIL= 100 A;
VCC= 1.65V to 5.5 V - 0.1 - 0.1 V =4mA; VCC = 1.65V - - 0.45 - 0.70 V =8mA; VCC = 2.3V - - 0.3 - 0.45 V =12mA; VCC = 2.7 V - - 0.4 - 0.60 V =24mA; VCC = 3.0 V - - 0.55 - 0.80 V =32mA; VCC = 4.5 V - - 0.55 - 0.80 V input leakage
current
VI = 5.5 V or GND;
VCC =0Vto5.5V 0.1 5- 100 A
NXP Semiconductors 74LVC1G00
Single 2-input NAND gate
[1] All typical values are measured at VCC=3.3 V and Tamb =25C.
11. Dynamic characteristics
[1] Typical values are measured at Tamb =25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs.
IOFF power-off
leakage
current
VCC = 0 V; VIorVO =5.5V - 0.1 10 - 200 A
ICC supply current VI = 5.5 V or GND; IO = 0 A;
VCC= 1.65Vto 5.5 V
-0.1 10 - 200 A
ICC additional
supply current
VCC = 2.3 V to 5.5 V; =VCC 0.6 V; IO =0 A;
perpin 5 500 - 5000 A input
capacitance
VCC =3.3 V; VI = GND to VCC -5 - - - pF
Table 7. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground=0V).
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground=0 V); for load circuit see Figure9.
tpd propagation delay A, Bto Y; see Figure8 [2]
VCC= 1.65 V to 1.95V 1.0 3.3 8.0 1.0 10.5 ns
VCC= 2.3 V to 2.7V 0.5 2.2 5.5 0.5 7.0 ns
VCC= 2.7V 0.5 2.6 5.8 0.5 7.5 ns
VCC= 3.0 V to 3.6V 0.5 2.2 4.7 0.5 6.0 ns
VCC= 4.5 V to 5.5V 0.5 1.8 4.0 0.5 5.5 ns
CPD power dissipation
capacitance
VI = GND to VCC;
VCC= 3.3 V
[3] -14- - - pF
NXP Semiconductors 74LVC1G00
Single 2-input NAND gate
12. Waveforms
Table 9. Measurement points
1.65 V to 1.95V 0.5VCC 0.5VCC
2.3 V to 2.7V 0.5VCC 0.5VCC
2.7V 1.5V 1.5V
3.0V to 3.6V 1.5V 1.5V
4.5 V to 5.5V 0.5VCC 0.5VCC
NXP Semiconductors 74LVC1G00
Single 2-input NAND gate
Table 10. Test data
1.65 V to 1.95V VCC  2.0ns 30pF 1k open
2.3 V to 2.7V VCC  2.0ns 30pF 500 open
2.7V 2.7V  2.5ns 50pF 500 open
3.0V to 3.6V 2.7V  2.5ns 50pF 500 open
4.5 V to 5.5V VCC  2.5ns 50pF 500 open
NXP Semiconductors 74LVC1G00
Single 2-input NAND gate
13. Package outline
NXP Semiconductors 74LVC1G00
Single 2-input NAND gate

Partno	Mfg	Dc	Qty	Available	Descript
74LVC1G00GF	NXP	N/a	1700	avai	Single 2-input NAND-gate
74LVC1G00GM	NXP	N/a	600	avai	74LVC1G00; Single 2-input NAND gate
74LVC1G00GW	NXP	N/a	43500	avai	Single 2-input NAND gate