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74LVC163D-74LVC163DB-74LVC163PW
Presettable synchronous 4-bit binary counter; synchronous reset
Product specification
Supersedes data of 1996 Aug 23
IC24 Data Handbook
1998 May 20
Philips Semiconductors Product specification
74LVC163Presettable synchronous 4-bit binary counter;
synchronous reset
FEATURES Wide supply voltage range of 1.2 V to 3.6 V In accordance with JEDEC standard no. 8–1A Inputs accept voltages up to 5.5V CMOS low power consumption Direct interface with TTL levels Synchronous reset Synchronous counting and loading Two count enable inputs for n–bit cascading Positive edge–triggered clock
DESCRIPTIONThe 74LVC163 is a high-performance, low-power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
The 74LVC163 is a synchronous presettable binary counter which
features an internal look–head carry and can be used for high-speed
counting. Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the clock (CP).
The outputs (Q0to Q3) of the counters may be preset to a HIGH or
LOW level. A LOW level at the parallel enable input (PE) disables
the counting action and causes the data at the data inputs
(D0to D3) to be loaded into the counter on the positive–going edge
of the clock (provided that the set-up and hold time requirements for
PE are met). Preset takes place regardless of the levels at count
enable inputs (CEP and CET). A low level at the master reset input
(MR) sets all four outputs of the flip-flops (Q0to Q3) to LOW level
after the next positive-going transition on the clock (CP) input
(provided that the set-up and hold time requirements for PE are
met).
This action occurs regardless of the levels at CP, PE, CET and CEP
inputs This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND gate.
The look–ahead carry simplifies serial cascading of the counters.
Both count enable inputs (CEP and CET) must be HIGH to count.
The CET input is fed forward to enable the terminal count output
(TC). The TC output thus enabled will produce a HIGH output pulse
of a duration approximately equal to a HIGH level output of Q0. This
pulse can be used to enable the next cascaded stage. The
maximum clock frequency for the cascaded counters is determined
by the CP to TC propagation delay and CEPto CP set–up time,
according to the following formula:
fmax = 1 _______________________________
tp(max) (CP to TC) + tSU (CEP to CP)
QUICK REFERENCE DATAGND = 0V; Tamb = 25°C; TR = TF 2.5ns
NOTES: CPD is used to determine the dynamic power dissipation (PD in μW)
PD = CPD x VCC2 x fi +Σ (CL x VCC2 x fo ) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL x VCC2 x fo ) = sum of the outputs The condition is V1 = GND to VCC
ORDERING INFORMATION
Philips Semiconductors Product specification
74LVC163Presettable synchronous 4-bit binary counter;
synchronous reset
PIN CONFIGURATION
LOGIC SYMBOL
PIN DESCRIPTION
LOGIC SYMBOL (IEEE/IEC)
Philips Semiconductors Product specification
74LVC163Presettable synchronous 4-bit binary counter;
synchronous reset
FUNCTIONAL DIAGRAM
STATE DIAGRAM
FUNCTION TABLE
NOTES: = The TC output is High when CET is High and the counter
is at Terminal Count (HHHH) = High voltage level = High voltage level one setup time prior to the Low-to-High
clock transition = Low voltage level = Low voltage level one setup time prior to the Low-to-High
clock transition = Lower case letters indicate the state of the referenced
output one setup time prior to the Low-to-High clock
transition = Don’t care = Low-to-High clock transition
TYPICAL TIMING SEQUENCE
Typical timing sequence: reset outputs to zero; preset to binary
twelve; count to thirteen, fourteen, fifteen, zero, one, and two;
inhibit
Philips Semiconductors Product specification
74LVC163Presettable synchronous 4-bit binary counter;
synchronous reset
LOGIC DIAGRAM
Philips Semiconductors Product specification
74LVC163Presettable synchronous 4-bit binary counter;
synchronous reset
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS1In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
