74LVCH16374ADGG ,16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-stateFeatures and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply volt ..
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74LVC16374ADGG-74LVCH16374ADGG
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
1. General descriptionThe 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring
separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state
outputs for bus-oriented applications. It consists of two sections of eight positive
edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for
each octal.
The flip-flops store the state of their individual D-inputs that meet the set-up and hold time
requirements on the LOW-to-HIGH clock (CP) transition.
When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin
nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE
does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed 3.3 V and V applications.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused
inputs.
2. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Multibyte flow-through standard pinout architecture Low inductance multiple supply pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold (74LVCH16374A only) High-impedance outputs when VCC = 0 V Complies with JEDEC standard: JESD8-7A (1.65Vto 1.95V) JESD8-5A (2.3Vto 2.7V) JESD8-C/JESD36 (2.7Vto 3.6V) ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-B exceeds 200V CDM JESD22-C101E exceeds 1000V Specified from 40 C to +85 C and 40 C to +125 C
74L VC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
Rev. 11 — 16 January 2013 Product data sheet
NXP Semiconductors 74L VC16374A; 74L VCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information 74LVC16374ADL 40 Cto +125C SSOP48 plastic shrink small outline package; 48 leads;
body width 7.5 mm
SOT370-1
74LVCH16374ADL
74LVC16374ADGG 40 Cto +125C TSSOP48 plastic thin shrink small outline package; leads; body width 6.1 mm
SOT362-1
74LVCH16374ADGG
74LVC16374ABX 40 Cto +125C HXQFN60U plastic thermal enhanced extremely thin quad flat
package; no leads; 60 terminals; UTLP based;
body 4 6 0.5 mm
SOT1134-1
74LVCH16374ABX
NXP Semiconductors 74L VC16374A; 74L VCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-stateNXP Semiconductors 74L VC16374A; 74L VCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
5. Pinning information
5.1 PinningNXP Semiconductors 74L VC16374A; 74L VCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
NXP Semiconductors 74L VC16374A; 74L VCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
5.2 Pin description
6. Functional description[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition;
= LOW-to-HIGH transition;
Z = high-impedance OFF-state.
7. Limiting values
Table 2. Pin description1OE, 2OE 1, 24 A30, A13 output enable input (active LOW)
GND 4, 10, 15, 21, 28, 34, 39, 45 A32, A3, A8, A11, A16, A19, A24, A27 ground (0 V)
VCC 7, 18, 31, 42 A1, A10, A17, A26 supply voltage
1Q0 to 1Q7 2, 3, 5, 6, 8, 9, 11, 12 B20, A31, D5, D1, A2, B2, B3, A5 data output
2Q0 to 2Q7 13, 14, 16, 17, 19, 20, 22, 23 A6, B5, B6, A9, D2, D6, A12, B8 data output
1D0 to 1D7 47, 46, 44, 43, 41, 40, 38, 37 B18, A28, D8, D4, A25, B16, B15, A22 data input
2D0 to 2D7 36, 35, 33, 32, 30, 29, 27, 26 A21, B13, B12, A18, D3, D7, A15, B10 data input
1CP, 2CP 48, 25 A29, A14 clock input
Table 3. Function selection[1]Load and read register L lL L hH H
Load register and disable outputs H lL Z hH Z
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI <0V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO >VCC or VO <0V - 50 mA output voltage output HIGH-or LOW-state [2] 0.5 VCC +0.5 V
output 3-state [2] 0.5 +6.5 V output current VO =0 VtoVCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
NXP Semiconductors 74L VC16374A; 74L VCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] Above 60 C, the value of Ptot derates linearly with 5.5 mW/K.
[4] Above 70 C, the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
9. Static characteristicsPtot total power dissipation Tamb= 40 C to +125C
(T)SSOP48 package [3] -500 mW
HXQFN60U package [4] -1000 mW
Table 4. Limiting values …continuedIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Table 5. Recommended operating conditionsVCC supply voltage 1.65 - 3.6 V
functional 1.2 - - V input voltage 0 - 5.5 V output voltage active mode 0 - VCC V
power-down mode; VCC =0V 0 - 5.5 V
Tamb ambient temperature 40 - +125 C
t/V input transition rise and fall rate VCC= 1.65 V to 2.7V 0 - 20 ns/V
VCC= 2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristicsAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
VIH HIGH-level
input voltage
VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65 VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage
VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 VCC -0.35 VCCV
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
NXP Semiconductors 74L VC16374A; 74L VCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-stateVOH HIGH-level
output
voltage =VIHorVIL= 100 A;
VCC =1.65Vto3.6V
VCC 0.2 VCC -VCC 0.3 - V= 4mA; VCC = 1.65 V 1.2 - - 1.05 - V= 8mA; VCC = 2.3V 1.8 - - 1.65 - V= 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V= 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V= 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage =VIHorVIL= 100 A;
VCC= 1.65Vto 3.6 V 0 0.2 - 0.3 V =4mA; VCC = 1.65 V - - 0.45 - 0.65 V =8mA; VCC = 2.3V - - 0.6 - 0.8 V =12mA; VCC = 2.7 V - - 0.4 - 0.6 V =24mA; VCC = 3.0 V - - 0.55 - 0.8 V input leakage
current
VCC = 3.6 V; VI= 5.5Vor GND
[2] - 0.1 5- 20 A
IOZ OFF-state
output
current =VIHor VIL; VCC= 3.6 V; =5.5V orGND [2] - 0.1 5- 20 A
IOFF power-off
leakage
current
VCC = 0 V; VIorVO = 5.5V - 0.1 10 - 20 A
ICC supply
current
VCC = 3.6 V; VI =VCCor GND; =0A
-0.1 20 - 80 A
ICC additional
supply
current
per input pin;
VCC= 2.7Vto 3.6V; =VCC 0.6 V; IO =0A 5 500 - 5000 A input
capacitance
VCC= 0 V to 3.6V; =GNDto VCC
-5.0 - - - pF
IBHL bus hold
LOW current
VCC = 1.65; VI = 0.58 V [3][4] 10 - - 10 - A
VCC = 2.3; VI = 0.7 V 30 - - 25 - A
VCC = 3.0; VI = 0.8 V 75 - - 60 - A
IBHH bus hold
HIGH current
VCC = 1.65; VI = 1.07 V [3][4] 10 - - 10 - A
VCC = 2.3; VI = 1.7 V 30 - - 25 - A
VCC = 3.0; VI = 2.0 V 75 - - 60 - A
IBHLO bus hold
LOW
overdrive
current
VCC = 1.95 V [3][5] 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
Table 6. Static characteristics …continuedAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
NXP Semiconductors 74L VC16374A; 74L VCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state[1] All typical values are measured at VCC=3.3 V (unless stated otherwise) and Tamb =25C.
[2] The bus hold circuit is switched off when VI >VCC allowing 5.5 V on the input pin.
[3] Valid for data inputs (74LVCH16374A) only; control inputs do not have a bus hold circuit.
[4] The specified sustaining current at the data inputs holds the input below the specified VI level.
[5] The specified overdrive current at the data input forces the data input to the opposite logic input state.
10. Dynamic characteristicsIBHHO bus hold
HIGH
overdrive
current
VCC = 1.95 V [3][5] 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
Table 6. Static characteristics …continuedAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristicsVoltages are referenced to GND (ground=0 V). For test circuit see Figure 10.
tpd propagation
delay
nCP to nQn; see Figure7 [2]
VCC = 1.2 V - 14 - - - ns
VCC = 1.65 V to 1.95 V 2.1 6.9 13.5 2.1 15.6 ns
VCC = 2.3 V to 2.7 V 1.5 3.7 6.7 1.5 7.7 ns
VCC = 2.7 V 1.5 3.4 6.0 1.5 7.5 ns
VCC = 3.0 V to 3.6 V 1.5 3.1 5.4 1.5 7.0 ns
ten enable time nOE to nQn; see Figure9 [2]
VCC = 1.2 V - 20 - - - ns
VCC = 1.65 V to 1.95 V 1.5 5.9 13.1 1.5 15.1 ns
VCC = 2.3 V to 2.7 V 1.5 3.4 6.9 1.5 8.0 ns
VCC = 2.7 V 1.5 3.6 6.0 1.5 7.5 ns
VCC = 3.0 V to 3.6 V 1.0 2.7 5.2 1.0 6.5 ns
tdis disable time nOE to nQn; see Figure7 [2]
VCC = 1.2 V - 12 - - - ns
VCC = 1.65 V to 1.95 V 2.8 4.6 9.1 2.8 10.5 ns
VCC = 2.3 V to 2.7 V 1.0 2.5 4.9 1.0 5.7 ns
VCC = 2.7 V 1.5 3.4 5.1 1.5 6.5 ns
VCC = 3.0 V to 3.6 V 1.5 3.1 4.9 1.5 6.5 ns pulse width nCP HIGH; see Figure7
VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns
VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns
VCC = 2.7 V 3.0 - - 3.0 - ns
VCC = 3.0 V to 3.6 V 3.0 1.5 - 3.0 - ns
NXP Semiconductors 74L VC16374A; 74L VCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state[1] Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where: = input frequency in MHz; fo= output frequency in MHz= output load capacitance inpF
VCC= supply voltage in Volts= number of inputs switching
(CL VCC2fo)= sum of the outputs
tsu set-up time nDn to nCP; see Figure8
VCC = 1.65 V to 1.95 V 4.0 - - 4.0 - ns
VCC = 2.3 V to 2.7 V 3.0 - - 3.0 - ns
VCC = 2.7 V 1.9 - - 1.9 - ns
VCC = 3.0 V to 3.6 V 1.9 0.3 - 1.9 - ns hold time nDn to nCP; see Figure8
VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns
VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns
VCC = 2.7 V 1.1 - - 1.1 - ns
VCC = 3.0 V to 3.6 V +1.5 0.3 - 1.5 - ns
fmax maximum
frequency
see Figure7
VCC = 1.65 V to 1.95 V 100 - - 80 - ns
VCC = 2.3 V to 2.7 V 125 - - 100 - ns
VCC = 2.7 V 150 - - 120 - MHz
VCC = 3.0 V to 3.6 V 150 300 - 120 - MHz
tsk(o) output skew
time
VCC = 3.0 V to 3.6V [3] - - 1.0 - 1.5 ns
CPD power
dissipation
capacitance
per input; VI =GNDto VCC [4]
VCC = 1.65 V to 1.95 V - 14.1 - - - pF
VCC = 2.3 V to 2.7 V - 16.4 - - - pF
VCC = 3.0 V to 3.6 V - 18.5 - - - pF
Table 7. Dynamic characteristics …continuedVoltages are referenced to GND (ground=0 V). For test circuit see Figure 10.
