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74LVC16373-74LVC16373ADGG-74LVCH16373ADGG-74LVCH16373ADL
16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs 3-State
Product specification
Supersedes data of 1997 Aug 22
IC24 Data Handbook
1998 Mar 17
Philips Semiconductors Product specification
74LVC16373A/
74L VCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
FEATURES 5 volt tolerant inputs/outputs for interfacing with 5V logic Wide supply voltage range of 1.2V to 3.6V Complies with JEDEC standard no. 8-1A CMOS low power consumption MULTIBYTETM flow-through standard pin-out architecture Low inductance multiple power and ground pins for minimum
noise and ground bounce Direct interface with TTL levels All data inputs have bus hold (74LVCH167373A only) High impedance when VCC = 0
DESCRIPTIONThe 74LVC(H)16373A is a 16-bit D-type transparent latch featuring
separate D-type inputs for each latch and 3-State outputs for bus
oriented applications. One latch enable (LE) input and one output
enable (OE) are provided for each octal. Inputs can be driven from
either 3.3V or 5V devices. In 3-State operation, outputs can handle
5V. These features allow the use of these devices in a mixed
3.3V/5V environment.
The 74LVC(H)16373A consists of 2 sections of eight D-type
transparent latches with 3-State true outputs. When LE is HIGH,
data at the Dn inputs enter the latches. In this condition the latches
are transparent, i.e., a latch output will change each time its
corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
The 74LVCH16373A bus hold data inputs eliminates the need for
external pull up resistors to hold unused inputs.
PIN CONFIGURATION
QUICK REFERENCE DATAGND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns
NOTES: CPD is used to determine the dynamic power dissipation (PD in μW):
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
Philips Semiconductors Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
PIN DESCRIPTION
LOGIC SYMBOL
LOGIC DIAGRAM
FUNCTION TABLE (per section of eight bits) = HIGH voltage level = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition = LOW voltage level
Philips Semiconductors Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
LOGIC SYMBOL (IEEE/IEC)
BUS HOLD CIRCUIT
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
ABSOLUTE MAXIMUM RATINGS1In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICSOver recommended operating conditions voltages are referenced to GND (ground = 0V)
Philips Semiconductors Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
DC ELECTRICAL CHARACTERISTICS (Continued)Over recommended operating conditions voltages are referenced to GND (ground = 0V)
NOTES: All typical values are at VCC = 3.3V and Tamb = 25°C. Valid for data inputs of bus hold parts (LVCH16-A) only. For data inputs only, control inputs do not have a bus hold circuit. The specified sustaining current at the data input holds the input below the specified VI level. The specified overdrive current at the data input forces the data input to the opposite logic input state. For bus hold parts, the bus hold circuit is switched off when Vi exceeds VCC allowing 5.5V on the input terminal.
AC CHARACTERISTICSGND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C.
NOTE: All typical values are at VCC = 3.3V and Tamb = 25°C.
AC WAVEFORMSVM = 1.5V at VCC � 2.7V; VM = 0.5 VCC at VCC � 2.7V.
VOL and VOH are the typical output voltage drop that occur with the output load.
VX = VOL + 0.3V at VCC � 2.7V; VX = VOL + 0.1 VCC at VCC �2.7V
VY = VOH –0.3V at VCC �2.7V; VY = VOH – 0.1 VCC at VCC �2.7V
