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74LVC16245ADGG-74LVC16245ADL-74LVCH16245ADGG-74LVCH16245AEV
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
1. General descriptionThe 74LVC16245A; 74LVCH16245A are 16-bit transceivers featuring non-inverting
3-state bus compatible outputs in both send and receive directions. The device features
two output enable (nOE) inputs for easy cascading and two send/receive (nDIR) inputs for
direction control. nOE controls the outputs so that the buses are effectively isolated. This
device can be used as two 8-bit transceivers or one 16-bit transceiver.
Inputs can be driven from either 3.3Vor5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed
3.3V and5 V applications.
The 74LVCH16245A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
2. Features and benefits5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 Vto 3.6V CMOS low power consumption MULTIBYTE flow-through standard pin-out architecture Low inductance multiple power and ground pins for minimum noise and ground
bounce Direct interface with TTL levels High-impedance when VCC =0V All data inputs have bus hold (74LVCH16245A only) Complies with JEDEC standard: JESD8-7A (1.65Vto 1.95V) JESD8-5A (2.3Vto 2.7V) JESD8-C/JESD36 (2.7Vto 3.6V) ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-B exceeds 200V CDM JESD22-C101E exceeds 1000V Specified from 40 Cto+85C and 40 Cto+125C
74L VC16245A; 74L VCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
Rev. 12 — 13 February 2012 Product data sheet
NXP Semiconductors 74L VC16245A; 74L VCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information74LVC16245ADL 40Cto +125 C SSOP48 plastic shrink small outline package; 48 leads;
body width 7.5 mm
SOT370-1
74LVCH16245ADL
74LVC16245ADGG 40Cto +125C TSSOP48 plastic thin shrink small outline package; leads; body width 6.1 mm
SOT362-1
74LVCH16245ADGG
74LVC16245AEV 40Cto +125C VFBGA56 plastic very thin fine-pitch ball grid array package; balls; body 4.57 0.65 mm
SOT702-1
74LVCH16245AEV
74LVC16245ABX 40 Cto +125C HXQFN60 plastic compatible thermal enhanced extremely
thin quad flat package; no leads; 60 terminals;
body 4 6 0.5 mm
SOT1134-2
74LVCH16245ABX
NXP Semiconductors 74L VC16245A; 74L VCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-stateNXP Semiconductors 74L VC16245A; 74L VCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
5. Pinning information
5.1 PinningNXP Semiconductors 74L VC16245A; 74L VCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
NXP Semiconductors 74L VC16245A; 74L VCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
5.2 Pin description
6. Functional description[1] H= HIGH voltage level; L= LOW voltage level; X= don’t care; Z= high-impedance OFF-state.
Table 2. Pin description1DIR, 2DIR 1, 24 A1, K1 A30, A13 direction control input
1B0 to 1B7 2, 3, 5, 6, 8, 9, 11,
B2, B1, C2, C1, D2, D1,
E2, E1
B20, A31, D5, D1, A2,
B2, B3, A5
data input/output
2B0 to 2B7 13, 14, 16, 17, 19,
20, 22, 23
F1, F2, G1, G2, H1, H2,
J1, J2
A6, B5, B6, A9, D2, D6,
A12, B8
data input/output
GND 4, 10, 15, 21, 28,
34, 39, 45
B3, B4, D3, D4, G3, G4,
J3, J4
A32, A3, A8, A11, A16,
A19, A24, A27
ground (0V)
VCC 7, 18, 31, 42 C3, C4, H3, H4 A1, A10, A17, A26 supply voltage
1OE, 2OE 48, 25 A6, K6 A29, A14 output enable input (active LOW)
1A0 to 1A7 47, 46, 44, 43, 41,
40, 38, 37
B5, B6, C5, C6, D5, D6,
E5, E6
B18, A28, D8, D4, A25,
B16, B15, A22
data input/output
2A0 to 2A7 36, 35, 33, 32, 30,
29, 27, 26
F6, F5, G6, G5, H6, H5,
J6, J5
A21, B13, B12, A18, D3,
D7, A15, B10
data input/output
n.c. - A2, A3, A4, A5, K2, K3,
K4, K5
A4, A7, A20, A23, B1,
B4, B7, B9, B11, B14,
B17, B19
not connected
Table 3. Function table[1] L nAn = nBn inputs H inputs nBn = nAn Z Z
NXP Semiconductors 74L VC16245A; 74L VCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
7. Limiting values[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] Above 60 C the value of Ptot derates linearly with 5.5 mW/K.
[4] Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI <0V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO >VCC or VO <0V - 50 mA output voltage output HIGH or LOW [2] 0.5 VCC +0.5 V
output 3-state [2] 0.5 +6.5 V output current VO =0V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40 C to +125 C;
(T)SSOP48 package [3] -500 mW
VFBGA56 package [4] -1000 mW
HXQFN60 package [4] -1000 mW
Table 5. Recommended operating conditionsVCC supply voltage 1.65 - 3.6 V
functional 1.2 - 3.6 V input voltage 0 - 5.5 V output voltage output HIGH or LOW 0 - VCC V
output 3-state 0 - 5.5 V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VCC = 1.2 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
NXP Semiconductors 74L VC16245A; 74L VCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
9. Static characteristicsTable 6. Static characteristicsAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
VIH HIGH-level input
voltage
VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65 VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level input
voltage
VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 VCC - 0.35 VCCV
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output voltage =VIHorVIL= 100 A;
VCC =1.65Vto3.6V
VCC 0.2 - - VCC 0.3 - V= 4mA; VCC = 1.65 V 1.2 - - 1.05 - V= 8mA; VCC = 2.3V 1.8 - - 1.65 - V= 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V= 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V= 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level output
voltage =VIHorVIL= 100 A;
VCC= 1.65Vto 3.6 V 0.2 - 0.3 V =4mA; VCC = 1.65 V - - 0.45 - 0.65 V =8mA; VCC = 2.3V - - 0.6 - 0.8 V =12mA; VCC = 2.7 V - - 0.4 - 0.6 V =24mA; VCC = 3.0 V - - 0.55 - 0.8 V input leakage
current[2] VI =5.5V orGND;
VCC =3.6V 0.1 5- 20 A
IOZ OFF-state output
current [2][3] VI =VIHor VIL; = 5.5Vor GND;
VCC =3.6V 0.1 5- 20 A
IOFF power-off
leakage currentorVO =5.5 V; VCC = 0.0 V - 0.1 10 - 20 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =3.6V
-0.1 20 - 80 A
ICC additional supply
current
per input pin; VI =VCC 0.6V; =0A; VCC= 2.7 V to 3.6 V 5 500 - 5000 A input capacitance VCC= 0 V to 3.6V; =GNDto VCC
-5.0 - - - pF
CI/O input/output
capacitance
VCC= 0 V to 3.6V; =GNDto VCC
-10 - - - pF
NXP Semiconductors 74L VC16245A; 74L VCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25C.
[2] The bus hold circuit is switched off when VI >VCC allowing 5.5 V on the input terminal.
[3] For I/O ports the parameter IOZ includes the input leakage current.
[4] Valid for data inputs of bus hold parts only (74LVCH16245A). Note that control inputs do not have a bus hold circuit.
[5] The specified sustaining current at the data input holds the input below the specified VI level.
[6] The specified overdrive current at the data input forces the data input to the opposite input state.
10. Dynamic characteristicsIBHL bus hold LOW
current [4][5] VCC = 1.65; VI = 0.58 V 10 - - 10 - A
VCC = 2.3; VI = 0.7 V 30 - - 25 - A
VCC = 3.0; VI = 0.8 V 75 - - 60 - A
IBHH bus hold HIGH
current [4][5] VCC = 1.65; VI = 1.07 V 10 - - 10 - A
VCC = 2.3; VI = 1.7 V 30 - - 25 - A
VCC = 3.0; VI = 2.0 V 75 - - 60 - A
IBHLO bus hold LOW
overdrive current
[4][6]
VCC = 1.95 V 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
IBHHO bus hold HIGH
overdrive current
[4][6]
VCC = 1.95 V 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
Table 6. Static characteristics …continuedAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristicsVoltages are referenced to GND (ground=0 V). For test circuit see Figure9.
tpd propagation
delay
nAnto nBn; nBnto nAn; see Figure7 [1]
VCC= 1.2V - 13.0 - - - ns
VCC = 1.65 V to 1.95 V 1.5 5.2 12.2 1.5 13.8 ns
VCC = 2.3 V to 2.7 V 1.0 2.8 6.0 1.0 6.7 ns
VCC = 2.7 V 1.0 2.7 4.7 1.0 6.0 ns
VCC = 3.0 V to 3.6 V 1.0 2.4 4.5 1.0 6.0 ns
ten enable time nOEto nAn, nBn; see Figure8 [1]
VCC= 1.2V - 15.0 - - - ns
VCC = 1.65 V to 1.95 V 1.5 5.9 15.0 1.5 16.9 ns
VCC = 2.3 V to 2.7 V 1.0 3.3 7.9 1.0 8.8 ns
VCC = 2.7 V 1.5 3.5 6.7 1.5 8.5 ns
VCC = 3.0 V to 3.6 V 1.0 2.7 5.5 1.0 7.0 ns
NXP Semiconductors 74L VC16245A; 74L VCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state[1] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[2] Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[3] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fiN+ (CL VCC2fo) where: = input frequency in MHz; fo= output frequency in MHz= output load capacitance inpF
VCC= supply voltage in Volts= number of inputs switching
(CL VCC2fo)= sum of the outputs.
11. Waveformstdis disable time nOEto nAn, nBn; see Figure8 [1]
VCC= 1.2V - 11.0 - - - ns
VCC = 1.65 V to 1.95 V 1.0 4.9 13.1 1.0 14.7 ns
VCC = 2.3 V to 2.7 V 0.5 2.7 7.1 0.5 7.9 ns
VCC = 2.7 V 1.5 3.4 6.6 1.5 8.5 ns
VCC = 3.0 V to 3.6 V 1.5 3.3 5.6 1.5 7.0 ns
CPD power
dissipation
capacitance
per input; VI =GNDto VCC [3]
VCC = 1.65 V to 1.95 V - 11.5 - - - pF
VCC = 2.3 V to 2.7 V - 15.2 - - - pF
VCC = 3.0 V to 3.6 V - 18.5 - - - pF
Table 7. Dynamic characteristics …continuedVoltages are referenced to GND (ground=0 V). For test circuit see Figure9.
