SN74LVC161284DGGR ,19-Bit Bus Interface With 3-State Outputs/sc/package.FUNCTION TABLEINPUTSOUTPUT OUTPUT MODE MODEDIR HDOpen drain A9−A13 to Y9−Y13 and PERI L ..
SN74LVC161284DL ,19-Bit Bus Interface With 3-State OutputsElectrical SpecificationsV 7 42 V CABLECC CC Flow-Through Architecture Optimizes PCBA1 8 41 B1Layo ..
SN74LVC161284DLG4 ,19-Bit Bus Interface With 3-State Outputs 48-SSOP 0 to 70 SCAS583J − NOVEMBER 1996 − REVISED FEBRUARY 2005DGG OR DL PACKAGE 1 ..
SN74LVC161284DLR ,19-Bit Bus Interface With 3-State Outputslogic diagram42V CABLECCSee Note B48DIRSee Note B1HDSee Note AA1−A8B1−B8A9−A13 Y9−Y1319 30PERI LOGI ..
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74LVC161284DGGRG4-74LVC161284DLRG4-SN74LVC161284-SN74LVC161284DGGR-SN74LVC161284DL-SN74LVC161284DLG4-SN74LVC161284DLR
19-Bit Bus Interface With 3-State Outputs 48-TSSOP 0 to 70
Using Machine Model (C = 200 pF, R = 0) Designed for the IEEE Std 1284-I (Level 1
Type) and IEEE Std 1284-II (Level 2 Type)
Electrical Specifications Flow-Through Architecture Optimizes PCB
Layout Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin-Shrink
Small-Outline (DGG) Packages
description/ordering informationThe SN74LVC161284 is designed for 3-V to 3.6-VCC operation. This device provides
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
This device has eight bidirectional bits; data can
flow in the A-to-B direction when DIR is high and
in the B-to-A direction when DIR is low. This
device also has five drivers, which drive the cable
side, and four receivers. The SN74LVC161284
has one receiver dedicated to the HOST LOGIC
line and a driver to drive the PERI LOGIC line.
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in
a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive
requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level 2 type) parallel
peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have
a 1.4-kΩ integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low
state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.
The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs
and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even
when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.
The SN74LVC161284 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
A10
A11
A12
A13CC
GND
GND
VCC
PERI LOGIC IN
A14
A15
A16
A17
HOST LOGIC OUT
Y10
Y11
Y12
Y13CC CABLE
GND
GND
VCC CABLE
PERI LOGIC OUT
C14
C15
C16
C17
HOST LOGIC IN
