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74LVC157ADB-74LVC157APW-LVC157A
Quad 2-input multiplexer
Product specification
Supercedes data of 1997 Nov 07
IC24 Data Handbook
1998 Jul 29
Philips Semiconductors Product specification
74LVC157AQuad 2-input multiplexer
FEATURES Wide supply voltage range of 1.2 to 3.6 V In accordance with JEDEC standard no. 8-1A CMOS lower power consumption Direct interface with TTL levels 5 Volt tolerant inputs, for interfacing with 5 Volt logic
DESCRIPTIONThe 74LVC157A is a high-performance, low-power, Si-gate CMOS
device, superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC157A is a quad 2-input multiplexer which select 4 bits of
data from two sources under the control of a common data select
input (S). The four outputs present the selected data in the true
(non-inverted) form. The enable input (E) is active LOW. When E is
HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all
other input conditions. Moving the data from two groups of registers
to four common output buses is a common use of the 74LV157. The
state of the common data select input (S) determines the particular
register from which the data comes. It can also be used as function
generator.
The device is useful for implementing highly irregular logic by
generating any four of the 16 different functions of two variables with
one variable common.
The 74LVC157A is the logic implementation of a 4-pole, 2-position
switch, where the position of the switch is determined by the logic
levels applied to S.
QUICK REFERENCE DATAGND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
NOTES: CPD is used to determine the dynamic power dissipation (PD in μW)
PD = CPD × VCC 2 × fi Σ (CL × VCC 2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL × VCC 2 × fo) = sum of the outputs.
ORDERING INFORMATION
PIN CONFIGURATION
PIN DESCRIPTION
Philips Semiconductors Product specification
74LVC157AQuad 2-input multiplexer
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
FUNCTIONAL DIAGRAM
FUNCTION TABLE
NOTES:= HIGH voltage level= LOW voltage level= don’t care
LOGIC DIAGRAM
Philips Semiconductors Product specification
74LVC157AQuad 2-input multiplexer
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS1In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors Product specification
74LVC157AQuad 2-input multiplexer
DC ELECTRICAL CHARACTERISTICSOver recommended operating conditions. Voltages are referenced to GND (ground = 0V).
NOTE: All typical values are measured at VCC = 3.3V and Tamb = 25°C.
AC CHARACTERISTICSGND = 0 V; tr = tf � 2.5 ns; CL = 50 pF; RL = 500; Tamb = –40C to +85C
NOTE: These typical values are at VCC = 3.3V and Tamb = 25°C.
Philips Semiconductors Product specification
74LVC157AQuad 2-input multiplexer
AC WAVEFORMSVM = 0.5 × VCC at VCC < 2.7 V
VM = 1.5 V at VCC ≥ 2.7 V
VX = VOL + 0.3 V at VCC ≥ 2.7 V
VX = VOL + 0.1 × VCC at VCC < 2.7 V
VY = VOH – 0.3 V at VCC ≥ 2.7V
VY = VOH – 0.1 × VCC at VCC < 2.7 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
Figure 1. Enable input (E) to output (nY) propagation delays.
Figure 2. Data inputs (nI0, nI1) and common data select
input (S) to output (nY) propagation delays.
TEST CIRCUIT
Figure 3. Load circuitry for switching times.
