74LVC138ABQ -74LVC138APW Fast Delivery |IC PHOENIX CO.,LIMITED

74LVC138APW ,3-to-8 line decoder/demultiplexer; invertingPin configuration for SO16 and (T)SSOP16 Fig 5.
74LVC138APWDH ,3-to-8 line decoder/demultiplexer; invertingfeatures three enable inputs: two active LOW (E1and E ) and one active HIGH (E ). Every output will ..
74LVC139 ,Dual 2-to-4 line decoder/demultiplexer
74LVC139 ,Dual 2-to-4 line decoder/demultiplexer
74LVC139 ,Dual 2-to-4 line decoder/demultiplexer
74LVC139D ,Dual 2-to-4 line decoder/demultiplexerPIN CONFIGURATION PIN DESCRIPTIONPIN NUMBER SYMBOL NAME AND FUNCTIONV1 16 CC1E1, 15 1E, 2E Enable i ..
8035AHL , HMOS SINGLE-COMPONENT 8-BIT MICROCONTROLLER
8041-05-011 , DIP Reed Relays
8049AH , HMOS SINGLE-COMPONENT 8-BIT MICROCONTROLLER
8080A , 8-Bit Microprocessor
8085AH-2 , 8-Bit HMOS MICROPROCESSORS 3MHz, 5 MHz and 6 MHz Selections Avallable
80C186 , CMOS High-Integration 16-Bit Microprocessors

74LVC138ABQ -74LVC138APW
3-to-8 line decoder/demultiplexer; inverting
1. General description
The 74LVC138A is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted
address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive
outputs (Y0to Y7) that are LOW when selected.
There are three enable inputs: two active LOW (E1andE2) and one active HIGH (E3).
Every output will be HIGH unless E1andE2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the device to a 1-of-32 linesto32 lines) decoder with just four 74LVC138A devices and one inverter. The
74LVC138A can be used as an eight output demultiplexer by using one of the active LOW
enable inputs as the data input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their appropriate active HIGH or LOW state.
2. Features and benefits5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6V CMOS low power consumption Direct interface with TTL levels Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding Mutually exclusive outputs Output drive capability 50  transmission lines at 125C Complies with JEDEC standard: JESD8-7A (1.65Vto 1.95V) JESD8-5A (2.3Vto 2.7V) JESD8-C/JESD36 (2.7Vto 3.6V) ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-B exceeds 200V CDM JESD22-C101E exceeds 1000V Specified from 40 Cto+85 C and from 40 C to +125C
74L VC138A
3-to-8 line decoder/demultiplexer; inverting
Rev. 5 — 19 October 2011 Product data sheet
NXP Semiconductors 74L VC138A
3-to-8 line decoder/demultiplexer; inverting
3. Ordering information
4. Functional diagram
Table 1. Ordering information
74LVC138AD 40 Cto +125C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74LVC138ADB 40 Cto +125C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74LVC138APW 40 Cto +125C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74LVC138ABQ 40 Cto +125C DHVQFN16 plastic dual in-line compatible thermal-enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 3.5  0.85 mm
SOT763-1
NXP Semiconductors 74L VC138A
3-to-8 line decoder/demultiplexer; inverting
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 address input 2 address input 3 address input 4 enable input (active LOW) 5 enable input (active LOW) 6 enable input (active HIGH)
GND 8 ground (0V)
Y[0:7] 15, 14, 13, 12, 11, 10, 9, 7 output
VCC 16 supply voltage
NXP Semiconductors 74L VC138A
3-to-8 line decoder/demultiplexer; inverting
6. Functional description
[1] H= HIGH voltage level; L= LOW voltage level; X= don’t care
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO16 packages: above 70 C the value of PD derates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60 C the value of PD derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of PD derates linearly with 4.5 mW/K.
Table 3. Function table[1]
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI <0 V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO >VCC or VO <0 V - 50 mA output voltage output HIGH or LOW state [2] 0.5 VCC +0.5 V output current VO =0 VtoVCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40Cto +125C [3] -500 mW
NXP Semiconductors 74L VC138A
3-to-8 line decoder/demultiplexer; inverting
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
VCC supply voltage 1.65 - 3.6 V
functional 1.2 - - V input voltage 0 - 5.5 V output voltage output HIGH or LOW state 0 - VCC V
Tamb ambient temperature 40 - +125 C
t/V input transition rise and fall
rate
VCC= 1.65Vto 2.7V 0 - 20 ns/V
VCC= 2.7Vto 3.6V 0 - 10 ns/V
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
VIH HIGH-level
input voltage
VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65  VCC- - 0.65  VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage
VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35  VCC -0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage =VIHorVIL= 100 A;
VCC =1.65Vto3.6V
VCC 0.2 - - VCC 0.3 - V= 4mA; VCC = 1.65 V 1.2 - - 1.05 - V= 8mA; VCC = 2.3V 1.8 - - 1.65 - V= 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V= 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V= 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage =VIHorVIL= 100 A;
VCC= 1.65Vto 3.6 V - 0.2 - 0.3 V =4mA; VCC = 1.65 V - - 0.45 - 0.65 V =8mA; VCC = 2.3V - - 0.6 - 0.8 V =12mA; VCC = 2.7 V - - 0.4 - 0.6 V =24mA; VCC = 3.0 V - - 0.55 - 0.8 V input leakage
current
VCC = 3.6 V; VI =5.5V orGND- 0.1 5- 20 A
NXP Semiconductors 74L VC138A
3-to-8 line decoder/demultiplexer; inverting
[1] All typical values are measured at VCC=3.3 V (unless stated otherwise) and Tamb =25C.
10. Dynamic characteristics
ICC supply
current
VCC = 3.6 V; VI =VCCor GND; =0A
-0.1 10 -40 A
ICC additional
supply
current
per input pin;
VCC= 2.7Vto 3.6V; =VCC 0.6 V; IO =0A 5 500 - 5000 A input
capacitance
VCC= 0 V to 3.6V; =GNDto VCC 4.0 -- -pF
Table 6. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground=0 V). For test circuit see Figure8.
tpd propagation delay Anto Yn; see Figure6 [2]
VCC = 1.2 V - 14 - - - ns
VCC = 1.65 V to 1.95 V 0.5 5.2 11.5 0.5 12.7 ns
VCC = 2.3 V to 2.7 V 1.5 3.0 6.5 1.5 7.3 ns
VCC = 2.7V 1.5 3.2 6.8 1.5 8.5 ns
VCC = 3.0 V to 3.6V 1.0 2.7 5.8 1.0 7.5 nsto Yn; see Figure6 [2]
VCC = 1.2 V - 14 - - - ns
VCC = 1.65 V to 1.95 V 1.0 5.5 11.4 1.0 12.5 ns
VCC = 2.3 V to 2.7 V 1.5 3.2 6.5 1.5 7.1 ns
VCC = 2.7V 1.5 3.3 6.8 1.5 8.5 ns
VCC = 3.0 V to 3.6V 1.0 2.9 5.8 1.0 7.5 ns
Ento Yn; see Figure7 [2]
VCC = 1.2 V - 15 - - - ns
VCC = 1.65 V to 1.95 V 1.0 5.6 11.5 1.0 12.8 ns
VCC = 2.3 V to 2.7 V 1.8 3.3 6.5 1.8 7.3 ns
VCC = 2.7V 1.5 3.4 6.4 1.5 8.0 ns
VCC = 3.0 V to 3.6V 1.0 2.9 5.8 1.0 7.5 ns
tsk(o) output skew time [3] - - 1.0 - 1.5 ns
NXP Semiconductors 74L VC138A
3-to-8 line decoder/demultiplexer; inverting
[1] Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where:= input frequency in MHz; fo= output frequency in MHz= output load capacitance inpF
VCC= supply voltage in V= number of inputs switching
(CL VCC2fo)= sum of outputs
11. Waveforms
CPD power dissipation
capacitance
VI = GND to VCC [4]
VCC = 1.65 V to 1.95 V - 9.9 - pF
VCC = 2.3 V to 2.7 V - 15.8 - pF
VCC = 3.0 V to 3.6 V - 21.1 - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V). For test circuit see Figure8.
NXP Semiconductors 74L VC138A
3-to-8 line decoder/demultiplexer; inverting
Table 8. Test data
1.2V VCC  2 ns 30pF 1 k
1.65Vto 1.95V VCC  2 ns 30pF 1 k
2.3Vto 2.7V VCC  2 ns 30pF 500
2.7V 2.7V  2.5ns 50pF 500
3.0Vto 3.6V 2.7V  2.5ns 50pF 500

Partno	Mfg	Dc	Qty	Available	Descript
74LVC138ABQ \|74LVC138ABQ	NXP	N/a	5913	avai	3-to-8 line decoder/demultiplexer; inverting
74LVC138APW	NXP	N/a	20010	avai	3-to-8 line decoder/demultiplexer; inverting