74LVC125ATTR ,LOW VOLTAGE CMOS QUAD BUS BUFFERS HIGH PERFORMANCE74LVC125ALOW VOLTAGE CMOS QUAD BUS BUFFERS (3-STATE)HIGH PERFORMANCE■ 5V TOLERANT INPUTS■ HIGH SPEE ..
74LVC125ATTR ,LOW VOLTAGE CMOS QUAD BUS BUFFERS HIGH PERFORMANCEABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Supply Voltage-0.5 to +7.0 VCCV DC Input Volta ..
74LVC125D ,Quad buffer/line driver; 3-State
74LVC125PW ,Quad buffer/line driver; 3-State
74LVC125PW ,Quad buffer/line driver; 3-State
74LVC126A ,QUADRUPLE 3-STATE BUFFERS
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74LVC125AM-74LVC125ATTR
LOW VOLTAGE CMOS QUAD BUS BUFFERS HIGH PERFORMANCE
1/9December 2002 5V TOLERANT INPUTS HIGH SPEED: tPD= 4.8ns (MAX.)at VCC =3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:OH|=IOL= 24mA (MIN)atVCC =3V PCI BUS LEVELS GUARANTEED AT24 mA BALANCED PROPAGATION DELAYS:
tPLH≅ tPHL OPERATING VOLTAGE RANGE:CC (OPR)= 1.65Vto 3.6V (1.2V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH SERIES 125 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM> 2000V (MIL STD 883 method 3015);> 200V
DESCRIPTIONThe 74LVC125Aisa low voltage CMOS QUAD
BUS BUFFER fabricated with sub-micron silicon
gate and double-layer metal wiring C2 MOS
technology.It is ideal for 1.65 to 3.6VCCoperations and low power and low noise
applications. can be interfacedto 5V signal environment for
inputsin mixed 3.3/5V system.
These devices require the same 3-STATE control
inputGtobe taken highto make the outputgoin the high impedance state. has more speed performanceat 3.3V than 5V
AC/ACT family, combined witha lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVC125ALOW VOLTAGE CMOS QUAD BUS BUFFERS (3-STATE)
HIGH PERFORMANCE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74LVC125A2/9
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION TRUTH TABLE: Don’t care: High Impedance
ABSOLUTE MAXIMUM RATINGSAbsoluteMaximum Ratingsare those values beyond which damagetothe device mayoccur.Functional operation under these conditionsis
not impliedIO absolute maximum rating mustbe observedVO
74LVC125A
3/9
RECOMMENDED OPERATING CONDITIONS Truth Table guaranteed: 1.2Vto 3.6VVIN from 0.8Vto2Vat VCC =3.0V SPECIFICATIONS
74LVC125A
4/9
DYNAMIC SWITCHING CHARACTERISTICS Numberof output definedas"n". Measured with "n-1" outputs switching from HIGHto LOWor LOWto HIGH. The remaining outputis
measuredinthe LOW state. ELECTRICAL CHARACTERISTICS Skewis defined astheabsolute value ofthedifference betweenthe actual propagation delayfor anytwo outputsofthe samedevice switch-
inginthe same direction, either HIGHor LOW (tOSLH =|tPLHm -tPLHn|, tOSHL =|tPHLm -tPHLn| Parameter guaranteedby design
CAPACITIVE CHARACTERISTICS CPD isdefinedasthe valueofthe IC’s internal equivalent capacitance whichis calculatedfrom theoperating current consumption without
load.(Referto Test Circuit). Average operatingcurrentcanbe obtainedbythe followingequation. ICC(opr) =CPD xVCCxfIN+ICC/n (per circuit)
74LVC125A
5/9
TEST CIRCUIT =ZOUTof pulse generator (typically 50Ω)
TEST CIRCUIT AND WAVEFORM SYMBOL VALUE
74LVC125A
6/9
WAVEFORM1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
