74LVC02ABQ-74LVC02APW Fast Delivery |IC PHOENIX CO.,LIMITED

74LVC02ABQ ,Quad 2-input NOR gate
74LVC02ABQ ,Quad 2-input NOR gateLogic diagram for one gate5. Pinning information5.1 Pinning terminal 1index area2 131A 4Y1B 3 12 4B ..
74LVC02AD ,Quad 2-input NOR gatePIN CONFIGURATION PIN DESCRIPTIONPINSYMBOL NAME AND FUNCTIONNUMBER1Y 1 14 VCC1, 4, 10, 13 1Y – 4Y D ..
74LVC02ADB ,Quad 2-input NOR gateINTEGRATED CIRCUITS74LVC02AQuad 2-input NOR gateProduct specification 1998 Apr 28Supersedes data of ..
74LVC02APW ,Quad 2-input NOR gatePin configuration SO14 and (T)SSOP14 Fig 5.
74LVC04A ,Hex inverterAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
80021012A ,Octal Bus Transceivers With 3-State OutputsLogic Diagram (Positive Logic)1DIR19OE2A118B1To Seven Other ChannelsCopyright 2016, Texas Instrume ..
8035AHL , HMOS SINGLE-COMPONENT 8-BIT MICROCONTROLLER
8041-05-011 , DIP Reed Relays
8049AH , HMOS SINGLE-COMPONENT 8-BIT MICROCONTROLLER
8080A , 8-Bit Microprocessor
8085AH-2 , 8-Bit HMOS MICROPROCESSORS 3MHz, 5 MHz and 6 MHz Selections Avallable

74LVC02ABQ-74LVC02APW
Quad 2-input NOR gate
1. General description
The 74LVC02A provides four 2-input NOR gates.
Inputs can be driven from either 3.3Vor5 V devices. This feature allows the use of these
devices as translators in mixed 3.3V and5 V applications.
2. Features and benefits5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 Vto 3.6V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65Vto 1.95V) JESD8-5A (2.3Vto 2.7V) JESD8-C/JESD36 (2.7Vto 3.6V) ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-B exceeds 200V CDM JESD22-C101E exceeds 1000V Specified from 40 Cto+85C and 40 Cto+125C
3. Ordering information
74L VC02A
Quad 2-input NOR gate
Rev. 8 — 16 November 2011 Product data sheet
Table 1. Ordering information
74LVC02AD 40 Cto +125C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LVC02ADB 40 Cto +125C SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74LVC02APW 40 Cto +125C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LVC02ABQ 40 Cto +125C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.53 0.85 mm
SOT762-1
NXP Semiconductors 74L VC02A
Quad 2-input NOR gate
4. Functional diagram
5. Pinning information
5.1 Pinning
NXP Semiconductors 74L VC02A
Quad 2-input NOR gate
5.2 Pin description
6. Functional description
[1] H= HIGH voltage level; L= LOW voltage level; X= don’t care
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO14 packages: above 70 C derate linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K.
Table 2. Pin description
1Y to 4Y 1, 4, 10, 13 data output
1A to 4A 2, 5, 8, 11 data input
1B to 4B 3, 6, 9,12 data input
GND 7 ground (0 V)
VCC 14 supply voltage
Table 3. Function table[1]
LLH L L
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA output voltage output in HIGH or LOW-state [2] 0.5 VCC + 0.5 V output current VO = 0 V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Ptot total power dissipation Tamb = 40 C to +125C [3]- 500 mW
Tstg storage temperature 65 +150 C
NXP Semiconductors 74L VC02A
Quad 2-input NOR gate
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
VCC supply voltage 1.65 - 3.6 V
functional 1.2 - - V input voltage 0 - 5.5 V output voltage output HIGH or LOW state 0 - VCC V
Tamb ambient temperature 40 - +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
VIH HIGH-level
input voltage
VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65  VCC- - 0.65  VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage
VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35  VCC -0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage =VIHorVIL= 100 A;
VCC =1.65Vto3.6V
VCC 0.2 - - VCC 0.3 - V= 4mA; VCC = 1.65 V 1.2 - - 1.05 - V= 8mA; VCC = 2.3V 1.8 - - 1.65 - V= 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V= 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V= 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage =VIHorVIL= 100 A;
VCC= 1.65Vto 3.6 V - 0.2 - 0.3 V =4mA; VCC = 1.65 V - - 0.45 - 0.65 V =8mA; VCC = 2.3V - - 0.6 - 0.8 V =12mA; VCC = 2.7 V - - 0.4 - 0.6 V =24mA; VCC = 3.0 V - - 0.55 - 0.8 V input leakage
current
VCC = 3.6 V; VI =5.5V orGND- 0.1 5- 20 A
NXP Semiconductors 74L VC02A
Quad 2-input NOR gate
[1] All typical values are measured at VCC=3.3 V (unless stated otherwise) and Tamb =25C.
10. Dynamic characteristics
[1] Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where: = input frequency in MHz; fo= output frequency in MHz= output load capacitance inpF
VCC= supply voltage in Volts= number of inputs switching
(CL VCC2fo)= sum of the outputs
ICC supply
current
VCC = 3.6 V; VI =VCCor GND; =0A
-0.1 10 -40 A
ICC additional
supply
current
per input pin;
VCC= 2.7Vto 3.6 V; =VCC 0.6 V; IO =0A 5 500 - 5000 A input
capacitance
VCC= 0 V to 3.6V; =GNDto VCC 4.0 -- -pF
Table 6. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground=0 V). For test circuit see Figure7.
tpd propagation delay nA,nBto nY; see Figure6 [2]
VCC =1.2V - 14 - - - ns
VCC= 1.65Vto 1.95V 0.5 4.0 8.6 0.5 10.1 ns
VCC= 2.3Vto 2.7V 1.0 2.4 4.9 1.0 5.7 ns
VCC= 2.7V 1.0 2.5 5.1 1.0 6.5 ns
VCC= 3.0 V to 3.6V 1.0 2.2 4.4 1.0 5.5 ns
tsk(o) output skew time VCC= 3.0 V to 3.6V [3] - - 1.0 - 1.5 ns
CPD power dissipation
capacitance
per gate; VI =GNDto VCC [4]
VCC = 1.65 V to 1.95 V - 2.5 - - - pF
VCC = 2.3 V to 2.7 V - 5.7 - - - pF
VCC = 3.0 V to 3.6 V - 8.5 - - - pF
NXP Semiconductors 74L VC02A
Quad 2-input NOR gate
11. AC waveforms
Table 8. Test data
1.2V VCC  2 ns 30pF 1 k
1.65Vto 1.95V VCC  2 ns 30pF 1 k
2.3Vto 2.7V VCC  2 ns 30pF 500
2.7V 2.7V  2.5ns 50pF 500
3.0Vto 3.6V 2.7V  2.5ns 50pF 500
NXP Semiconductors 74L VC02A
Quad 2-input NOR gate
12. Package outline

Partno	Mfg	Dc	Qty	Available	Descript
74LVC02ABQ	NXP	N/a	30000	avai	Quad 2-input NOR gate
74LVC02APW	TI	N/a	1802	avai	Quad 2-input NOR gate