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74LVC00AM-74LVC00AMTR-74LVC00ATTR
LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE HIGH PERFORMANCE
1/8February 2002 5V TOLERANT INPUTS HIGH SPEED: tPD = 4.3ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:CC (OPR) = 1.65V to 3.6V (1.2V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 00 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTIONThe 74LVC00A is a low voltage CMOS QUAD
2-INPUT NAND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C2 MOS
technology. It is ideal for 1.65 to 3.6 VCC
operations and low power and low noise
applications.
It can be interfaced to 5V signal environment for
inputs in mixed 3.3/5V system.
It has more speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVC00ALOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE
HIGH PERFORMANCE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74LVC00A2/8
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
74LVC00A3/8
RECOMMENDED OPERATING CONDITIONS 1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
DC SPECIFICATIONS
74LVC00A4/8
DYNAMIC SWITCHING CHARACTERISTICS 1) Number of output defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
AC ELECTRICAL CHARACTERISTICS 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
74LVC00A5/8
TEST CIRCUIT RT = ZOUT of pulse generator (typically 50Ω)
TEST CIRCUIT AND WAVEFORM SYMBOL VALUE
WAVEFORM: PROPAGATION DELAY (f=1MHz; 50% duty cycle)
