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74LV74D-74LV74N-74LV74PW -LV74
Dual D-type flip-flop with set and reset; positive-edge trigger
Product specification
Supersedes data of 1996 Nov 07
IC24 Data Handbook
1998 Apr 20
Philips Semiconductors Product specification
74LV74Dual D-type flip-flop with set and reset;
positive edge-trigger
FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V,
Tamb = 25°C Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V,
Tamb = 25°C Output capability: standard ICC category: flip-flops
DESCRIPTIONThe 74LV74 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT74.
The 74LV74 is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (SD) and (RD)
inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the
clock pulse. The D inputs must be stable one set-up time prior to the
LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATAGND = 0V; Tamb = 25°C; tr =tf 2.5 ns
NOTES: CPD is used to determine the dynamic power dissipation (PD in μW)
PD = CPD VCC 2 x fi (CL VCC 2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL VCC 2 fo) = sum of the outputs. The condition is VI = GND to VCC
ORDERING INFORMATION
PIN DESCRIPTION
FUNCTION TABLE = HIGH voltage level
Philips Semiconductors Product specification
74LV74Dual D-type flip-flop with set and reset;
positive edge-trigger
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
LOGIC SYMBOL
FUNCTIONAL DIAGRAM
Philips Semiconductors Product specification
74LV74Dual D-type flip-flop with set and reset;
positive edge-trigger
LOGIC DIAGRAM (ONE FLIP-FLOP)
RECOMMENDED OPERATING CONDITIONS
NOTE: The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
ABSOLUTE MAXIMUM RATINGS1, 2In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
Philips Semiconductors Product specification
74LV74Dual D-type flip-flop with set and reset;
positive edge-trigger
DC CHARACTERISTICSOver recommended operating conditions voltages are referenced to GND (ground = 0V)
NOTE: All typical values are measured at Tamb = 25°C.
Philips Semiconductors Product specification
74LV74Dual D-type flip-flop with set and reset;
positive edge-trigger
AC CHARACTERISTICSGND = 0V; tr = tf � 2.5ns; CL = 50pF; RL = 1KΩ
NOTE: Unless otherwise stated, all typical values are at Tamb = 25°C.
