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74LV574DB-74LV574PW
Octal D-type flip-flop; positive edge-trigger 3-State
Product specification
Supersedes data of 1997 Feb 03
IC24 Data Handbook
1998 Jun 10
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V Typical VOLP (output ground bounce) 0.8V at VCC = 3.3V,
Tamb = 25°C Typical VOHV (output VOH undershoot) 2V at VCC = 3.3V,
Tamb = 25°C Common 3-State output enable input Output capability: bus driver ICC category: MSI
DESCRIPTIONThe 74LV574 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT574.
The 74LV574 is an octal D-type flip–flop featuring separate D-type
inputs for each flip-flop and non-inverting 3-state outputs for bus
oriented applications. A clock (CP) and an output enable (OE) input
are common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that
meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition.
When OE is LOW, the contents of the eight flip-flops is available at
the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
QUICK REFERENCE DATAGND = 0V; Tamb = 25°C; tr =tf 2.5 ns
NOTES: CPD is used to determine the dynamic power dissipation (PD in μW)
PD = CPD VCC2 x fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL VCC 2 fo) = sum of the outputs. The condition is VI = GND to VCC
ORDERING AND PACKAGE INFORMATION
PIN DESCRIPTION
FUNCTION TABLE = HIGH voltage level = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
PIN CONFIGURATION
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
FUNCTIONAL DIAGRAM
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS1, 2In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
NOTES: The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
DC CHARACTERISTICS FOR THE LV FAMILYOver recommended operating conditions voltages are referenced to GND (ground = 0V)
NOTE: All typical values are measured at Tamb = 25°C.
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
AC CHARACTERISTICSGND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
NOTE: Unless otherwise stated, all typical values are at Tamb = 25°C. Typical value measured at VCC = 3.3V.
