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74LV573D-74LV573DB-74LV573PW
Octal D-type transparent latch 3-State
Product specification
Supersedes data of 1997 Jun 06
IC24 Data Handbook
1998 Jun 10
Philips Semiconductors Product specification
74LV573Octal D-type transparent latch (3-State)
FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0V to 3.6V Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V,
Tamb = 25°C Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V,
Tamb = 25°C Inputs and outputs on opposite sides of package allowing easy
interface with microprocessors Useful as input or output port for microprocessors/microcomputer Common 3-State output enable input Output capability: bus driver ICC category: MSI
DESCRIPTIONThe 74LV573 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT573.
The 74LV573 is an octal D-type transparent latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE)
input are common to all internal latches.
The ‘573’ consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
The ‘573’ is functionally identical to the ‘563’ and the ‘373’, but the
‘563’ has inverted outputs and the ‘373’ has a different pin
arrangement.
QUICK REFERENCE DATAGND = 0V; Tamb = 25°C; tr = tf 2.5 ns
NOTES: CPD is used to determine the dynamic power dissipation (PD in μW)
PD = CPD VCC 2 x fi (CL VCC 2 fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL VCC 2 fo) = sum of the outputs. The condition is VI = GND to VCC.
ORDERING AND PACKAGE INFORMATION
PIN DESCRIPTION
Philips Semiconductors Product specification
74LV573Octal D-type transparent latch (3-State)
FUNCTION TABLE = HIGH voltage level = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition = LOW voltage level = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition = High impedance OFF-state
PIN CONFIGURATION
LOGIC SYMBOL
Philips Semiconductors Product specification
74LV573Octal D-type transparent latch (3-State)
LOGIC SYMBOL (IEEE/IEC)
FUNCTIONAL DIAGRAM
LOGIC DIAGRAM
Philips Semiconductors Product specification
74LV573Octal D-type transparent latch (3-State)
ABSOLUTE MAXIMUM RATINGS1, 2In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
NOTE: The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
Philips Semiconductors Product specification
74LV573Octal D-type transparent latch (3-State)
DC CHARACTERISTICS FOR THE LV FAMILYOver recommended operating conditions voltages are referenced to GND (ground = 0V)
NOTE: All typical values are measured at Tamb = 25°C.
Philips Semiconductors Product specification
74LV573Octal D-type transparent latch (3-State)
AC CHARACTERISTICSGND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
NOTES:All typical values are measured at Tamb = 25°C Typical values are measured at VCC = 3.3V
