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74LV4094PW
74LV4094; 8-stage shift-and-store bus register
Product specification 1998 Jun 23
Philips Semiconductors Product specification
74LV40948-stage shift-and-store bus register
FEATURES Optimized for low voltage applications: 1.0 to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25°C Output capability: standard ICC category: MSI
Applications: Serial-to-parallel data conversion Remote control holding register
DESCRIPTIONThe 74LV4094 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT4094.
The 74LV4094 is an 8-stage serial shift register having a storage
latch associated with each stage for strobing data from the serial
input (D) to the parallel buffered 3-State outputs (QP0 to OP7). The
parallel outputs may be connected directly to the common bus lines.
Data is shifted on the positive-going clock (CP) transitions. The data
in each shift register is transferred to the storage register when the
strobe input (STR) is HIGH. Data in the storage register appears at
the outputs whenever the output enable input (OE) signal is HIGH.
Two serial outputs (QS1 and QS2) are available for cascading a
number of 74LV4094 devices. Data is available at QS1 on the
positive-going clock edges to allow high-speed operation in
cascaded systems in which the clock rise time is fast. The same
serial information is available at QS2 on the next negative going
clock edge and is for cascading 74LV4094 devices when the clock
rise time is slow.
QUICK REFERENCE DATAGND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns
NOTE: CPD is used to determine the dynamic power dissipation (PD in μW)
PD = CPD × VCC2 × fi (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of the outputs.
ORDERING INFORMATION
PIN CONFIGURATION
PIN DESCRIPTION
Philips Semiconductors Product specification
74LV40948-stage shift-and-store bus register
LOGIC SYMBOL
FUNCTIONAL DIAGRAM
LOGIC SYMBOL (IEEE/IEC)
LOGIC DIAGRAM
Philips Semiconductors Product specification
74LV40948-stage shift-and-store bus register
FUNCTION TABLE
NOTES: = HIGH voltage level = LOW voltage level = don’t care = high impedance OFF-state= no change = LOW-to–HIGH CP transition = HIGH-to-LOW CP transition
Q’6= the information in the 8th register stage is transferred to theth register stage and QSn clock edge.
TIMING DIAGRAM
Philips Semiconductors Product specification
74LV40948-stage shift-and-store bus register
ABSOLUTE MAXIMUM RATINGS NO TAG, NO TAGIn accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
NOTE: The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
Philips Semiconductors Product specification
74LV40948-stage shift-and-store bus register
DC ELECTRICAL CHARACTERISTICSOver recommended operating conditions, voltages are referenced to GND (ground = 0 V)
NOTE: All typical values are measured at Tamb = 25°C.
Philips Semiconductors Product specification
74LV40948-stage shift-and-store bus register
AC CHARACTERISTICSGND = 0 V; tr = tf ≤ 2.5ns; CL = 50pF
