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74LV4060PW
14-stage binary ripple counter with oscillator
Product specification 1998 Jun 23
Philips Semiconductors Product specification
74LV406014-stage binary ripple counter with oscillator
FEATURES Wide operating voltage: 1.0 to 5.5 V Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25C. Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb
= 25C. All active components on chip RC or crystal oscillator configuration Output capability: standard (except for RTC and CTC) ICC category: MSI
APPLICATIONS Control Counters Timers Frequency Dividers Time-delay circuits
DESCRIPTIONThe 74LV4060 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT4060.
The 74LV4060 is a 14-stage ripple-carry counter/divider and
oscillator with three oscillator terminals (RS, RTC and CTC), ten
buffered outputs (Q3 to Q9 and Q11 to Q13) and an overriding
asynchronous master reset (MR). The oscillator configuration allows
design of either RC or crystal oscillator circuits. The oscillator may
be replaced by an external clock signal at input RS. In this case,
keep the oscillator pins (RTC and CTC) floating.
The counter advances on the negative-going transition of RS. A
HIGH level on MR resets the counter (Q3 to Q9 and Q11 to
Q13= LOW), independent of the other input conditions.
QUICK REFERENCE DATAGND = 0 V; Tamb = 25C; tr = tf < 2.5 ns
NOTES: CPD is used to determine the dynamic power
dissipation (PD in W)
PD = CPD x VCC 2 x fi + (CL x VCC 2 x fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL x VCC 2 x fo) = sum of the outputs. The condition is V1 = GND to VCC For formula on dynamic power dissipation, see the
following pages.
ORDERING INFORMATION
Philips Semiconductors Product specification
74LV406014-stage binary ripple counter with oscillator
PIN DESCRIPTION
PIN CONFIGURATION
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
Philips Semiconductors Product specification
74LV406014-stage binary ripple counter with oscillator
DYNAMIC POWER DISSIPATIONGND = 0 V; Tamb = 25 C
NOTE: Where:fo= output frequencyin MHz; fosc= oscillator frequencyin MHz; (CL xVCC2 xfo)= sumof the outputs; CL= output load capacitancein pF; = timing capacitancein pF; VCC= supply voltageinV.
FUNCTIONAL DIAGRAM
LOGIC DIAGRAM
Philips Semiconductors Product specification
74LV406014-stage binary ripple counter with oscillator
TIMING DIAGRAM
ABSOLUTE MAXIMUM RATINGS1, 2In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors Product specification
74LV406014-stage binary ripple counter with oscillator
RECOMMENDED OPERATING CONDITIONS
NOTES: The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
DC CHARACTERISTICSOver operating conditions, voltages are referenced to GND (ground = 0 V)
Philips Semiconductors Product specification
74LV406014-stage binary ripple counter with oscillator
Philips Semiconductors Product specification
74LV406014-stage binary ripple counter with oscillator
Philips Semiconductors Product specification
74LV406014-stage binary ripple counter with oscillator
NOTE: All typical values are measured at Tamb = 25°C.
AC CHARACTERISTICSGND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 500Ω
