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74LV374D-74LV374PW
Octal D-type flip-flop; positive edge-trigger; 3-state
General descriptionThe 74LV374isan octal D-type flip-flop featuring separate D-type inputsfor each flip-flop
and 3-state outputsfor bus-oriented applications.A clock input (CP) andan output enable
input (OE) are common to all flip-flops. The 74L V374 is a low-voltage Si-gate CMOS
device and is pin and function compatible with 74HC374 and 74HCT374.
The eight flip-flops will store the stateof their individual D-inputs that meet the set-up and
hold times requirements on the LOW to HIGH CP transition.
When OEis LOW, the contentsof the eight flip-flopsis availableat the outputs. When OE HIGH, the outputsgoto the high-impedance OFF-state. Operationof the OE input does
not affect the state of the flip-flops.
Features Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25°C Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb =25°C ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V Common 3-state output enable input Multiple package options Specified from −40 °Cto+85 °C and from −40°Cto +125°C
Ordering information
74L V374
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 02 — 14 May 2009 Product data sheet
Table 1. Ordering information74LV374N −40°Cto +125°C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74LV374D −40°Cto +125°C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74LV374DB −40°Cto +125°C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
74LV374PW −40°Cto +125°C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
NXP Semiconductors 74L V374
Octal D-type flip-flop; positive edge-trigger; 3-state Functional diagram
NXP Semiconductors 74L V374
Octal D-type flip-flop; positive edge-trigger; 3-state Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 output enable input (active LOW)
Q0 to Q7 2, 5, 6, 9, 12, 15, 16, 19 data output
D0 to D7 3, 4, 7, 8, 13, 14, 17, 18 data input
GND 10 ground (0 V) 11 clock input (LOW to HIGH; edge triggered)
VCC 20 supply voltage
NXP Semiconductors 74L V374
Octal D-type flip-flop; positive edge-trigger; 3-state Functional description[1]H= HIGH voltage level= HIGH voltage level one set-up time prior to the LOW to HIGH CP transition= LOW voltage level= LOW voltage level one set-up time prior to the LOW to HIGH CP transition= high-impedance OFF-state= LOW to HIGH clock transition
Limiting values[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP20 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.
For SO20 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
Table 3. Function table[1]Load and read register L ↑ lL L ↑ hH H
Load register and disable
outputs ↑ lL Z ↑ hH Z
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5 V orVI >VCC+ 0.5V [1]- ±20 mA
IOK output clamping current VO< −0.5 V orVO >VCC+ 0.5V [1]- ±50 mA output current VO = −0.5 V to (VCC+ 0.5V) - ±35 mA
ICC supply current - 70 mA
IGND ground current −70 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb= −40°Cto +125°C [2]
DIP20 - 750 mW
SO20, SSOP20 and TSSOP20 - 500 mW
NXP Semiconductors 74L V374
Octal D-type flip-flop; positive edge-trigger; 3-state Recommended operating conditions[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC=1.0 V (with input levels GND or VCC).
Static characteristics
Table 5. Recommended operating conditionsVoltages are referenced to GND (ground = 0 V).
VCC supply voltage[1] 1.0 3.3 5.5 V input voltage 0 - VCC V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V
VCC = 2.0 V to 2.7 V - - 200 ns/V
VCC = 2.7 V to 3.6 V - - 100 ns/V
VCC = 3.6 V to 5.5 V - - 50 ns/V
Table 6. Static characteristicsAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
VIH HIGH-level input voltage VCC = 1.2 V 0.9 - - 0.9 - V
VCC = 2.0 V 1.4 - - 1.4 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC -V
VIL LOW-level input voltage VCC = 1.2 V - - 0.3 - 0.3 V
VCC = 2.0 V - - 0.6 - 0.6 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCCV
VOH HIGH-level output voltage VI = VIH or VIL
IO = −100 μA; VCC = 1.2V - 1.2 - - - V
IO = −100 μA; VCC = 2.0V 1.8 2.0 - 1.8 - V
IO = −100 μA; VCC = 2.7V 2.5 2.7 - 2.5 - V
IO = −100 μA; VCC = 3.0V 2.8 3.0 - 2.8 - V
IO = −100 μA; VCC = 4.5V 4.3 4.5 - 4.3 - V
IO = −8 mA; VCC = 3.0V 2.4 2.82 - 2.2 - V
IO = −16 mA; VCC = 4.5V 3.6 4.2 - 3.5 - V
NXP Semiconductors 74L V374
Octal D-type flip-flop; positive edge-trigger; 3-state[1] Typical values are measured at Tamb = 25°C.
10. Dynamic characteristicsVOL LOW-level output voltage VI = VIH or VIL
IO = 100 μA; VCC = 1.2V - 0 - - - V
IO = 100 μA; VCC = 2.0V - 0 0.2 - 0.2 V
IO = 100 μA; VCC = 2.7V - 0 0.2 - 0.2 V
IO = 100 μA; VCC = 3.0V - 0 0.2 - 0.2 V
IO = 100 μA; VCC = 4.5V - 0 0.2 - 0.2 V
IO = 8 mA; VCC = 3.0V - 0.20 0.40 - 0.50 V
IO = 16 mA; VCC = 4.5V - 0.35 0.55 - 0.65 V input leakage current VI =VCCor GND;
VCC= 5.5V - 1.0 - 1.0 μA
IOZ OFF-state output current VI =VIH or VIL; =VCCor GND;
VCC= 5.5V
--5 - 10 μA
ICC supply current VI = VCC or GND; IO = 0A;
VCC= 5.5V - 20 - 160 μA
ΔICC additional supply current per input; VI = VCC − 0.6V;
VCC= 2.7Vto 3.6V - 500 - 850 μA input capacitance - 3.5 - - - pF
Table 6. Static characteristics …continuedAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristicsVoltages are referenced to GND (ground=0 V). For test circuit see Figure 10.
tpd propagation delay CPto Qn; see Figure7 [2]
VCC = 1.2 V - 90 - - - ns
VCC = 2.0 V - 31 39 - 49 ns
VCC = 2.7 V - 23 29 - 36 ns
VCC = 3.0 V to 3.6 V; CL =15pF [3] -14- - - ns
VCC = 3.0 V to 3.6 V [3] - 17 23 - 29 ns
VCC = 4.5 V to 5.5 V - - 19 - 24 ns
ten enable time OEto Qn; see Figure8 [4]
VCC = 1.2 V - 75 - - - ns
VCC = 2.0 V - 26 34 - 43 ns
VCC = 2.7 V - 19 25 - 31 ns
VCC = 3.0 V to 3.6 V [3] - 14 20 - 25 ns
VCC = 4.5 V to 5.5 V - - 17 - 21 ns
NXP Semiconductors 74L V374
Octal D-type flip-flop; positive edge-trigger; 3-state[1] Typical values are measured at Tamb =25°C.
[2] tpd is the same as tPLH and tPHL.
[3] Typical value measured at VCC = 3.3 V.
[4] ten is the same as tPZH and tPZL.
[5] tdis is the same as tPHZ and tPLZ.
[6] CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi× N+ ∑(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
∑(CL× VCC2×fo)= sum of outputs.
tdis disable time OEto Qn; Figure8 [5]
VCC = 1.2 V - 80 - - - ns
VCC = 2.0 V - 29 39 - 48 ns
VCC = 2.7 V - 22 29 - 36 ns
VCC = 3.0 V to 3.6 V [3] - 17 24 - 29 ns
VCC = 4.5 V to 5.5 V [3] - - 20 - 24 ns pulse width CP , HIGH or LOW; see Figure7
VCC = 2.0 V 34 12 - 41 - ns
VCC = 2.7 V 25 9 - 30 - ns
VCC = 3.0 V to 3.6 V [3] 20 7 - 24 - ns
tsu set-up time Dn to CP; see Figure9
VCC = 1.2 V - 25 - - - ns
VCC = 2.0 V 22 9 - 26 - ns
VCC = 2.7 V 16 6 - 19 - ns
VCC = 3.0 V to 3.6 V [3] 13 5 - 15 - ns hold time Dn to CP; see Figure9
VCC = 1.2 V - −10 - - - ns
VCC = 2.0 V 5 −3- 5 - ns
VCC = 2.7 V 5 −2- 5 - ns
VCC = 3.0 V to 3.6 V [3] 5 −2- 5 - ns
fmax maximum
frequency
see Figure7
VCC= 2.0 V 15 40 - 12 - MHz
VCC= 2.7V 19 58 - 16 - MHz
VCC= 3.3 V; CL=15pF - 77 - - - MHz
VCC= 3.0Vto 3.6V [3] 24 70 - 20 - MHz
CPD power dissipation
capacitance=50 pF; fi = 1 MHz;= GNDto VCC
[6] 25 pF
Table 7. Dynamic characteristics …continuedVoltages are referenced to GND (ground=0 V). For test circuit see Figure 10.
NXP Semiconductors 74L V374
Octal D-type flip-flop; positive edge-trigger; 3-state
11. Waveforms
NXP Semiconductors 74L V374
Octal D-type flip-flop; positive edge-trigger; 3-state
Table 8. Measurement points< 2.7 V 0.5VCC 0.5VCC VOL + 0.3V VOH − 0.3V
2.7 V to 3.6V 1.5 V 1.5 V VOL + 0.3V VOH − 0.3V
≥ 4.5 V 0.5VCC 0.5VCC VOL + 0.3V VOH − 0.3V
