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74LV174D-74LV174PW
Hex D-type flip-flop with reset; positive-edge trigger
Product specification
Supersedes data of 1997 Apr 07
IC24 Data Handbook
1998 May 20
Philips Semiconductors Product specification
74LV174Hex D-type flip-flop with reset; positive edge-trigger
FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V,
Tamb = 25°C Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V,
Tamb = 25°C Output capability: standard ICC category: MSI
DESCRIPTIONThe 74LV174 is a low–voltage Si–gate CMOS device and is pin and
function compatible with the 74HC/HCT174.
The 74LV174 has six edge–triggered D–type flip–flops with
individual D inputs and Q outputs. The common clock (CP) and
master reset (MR) inputs load and reset (clear) all flip–flops
simultaneously.
The register is fully edge–triggered. The state of each D input, one
set–up time prior to the LOW–to–HIGH clock transition, is
transferred to the corresponding output of the flip–flop.
A LOW level on the MR input forces all outputs LOW, independently
of clock or data inputs.
The device is useful for applications requiring true outputs only and
clock and master reset inputs that are common to all storage
elements.
QUICK REFERENCE DATAGND = 0V; Tamb = 25°C; tr = tf 2.5 ns
NOTES: CPD is used to determine the dynamic power dissipation (PD in μW)
PD = CPD VCC2 x fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL VCC2 fo) = sum of the outputs. The condition is VI = GND to VCC
ORDERING INFORMATION
Philips Semiconductors Product specification
74LV174Hex D-type flip-flop with reset; positive edge-trigger
PIN CONFIGURATION
PIN DESCRIPTION
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
Philips Semiconductors Product specification
74LV174Hex D-type flip-flop with reset; positive edge-trigger
FUNCTIONAL DIAGRAM
FUNCTION TABLE = HIGH voltage level = HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition = Lower case letter indicates the state of referenced input
one set-up time prior to the LOW-to-HIGH CP transition = LOW–to–HIGH clock transition
RECOMMENDED OPERATING CONDITIONS
NOTES: The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
Philips Semiconductors Product specification
74LV174Hex D-type flip-flop with reset; positive edge-trigger
ABSOLUTE MAXIMUM RATINGS1, 2In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC CHARACTERISTICS FOR THE LV FAMILYOver recommended operating conditions voltages are referenced to GND (ground = 0V)
Philips Semiconductors Product specification
74LV174Hex D-type flip-flop with reset; positive edge-trigger
DC CHARACTERISTICS FOR THE LV FAMILY (Continued)Over recommended operating conditions voltages are referenced to GND (ground = 0V)
NOTE: All typical values are measured at Tamb = 25°C.
AC CHARACTERISTICSGND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 1KΩ
Philips Semiconductors Product specification
74LV174Hex D-type flip-flop with reset; positive edge-trigger
AC CHARACTERISTICS (Continued)GND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 1KΩ
NOTES: Unless otherwise stated, all typical values are at Tamb = 25°C. Typical value measured at VCC = 3.3V. Typical value measured at VCC = 5.0V.
AC WAVEFORMSVM = 1.5V at VCC � 2.7V � 3.6V
VM = 0.5V * VCC at VCC � 2.7V and � 4.5V
VOL and VOH are the typical output voltage drop that occur with the
output load.
Figure 1. The clock (CP) to output (Qn) propagation delays, the
clock pulse width, and the maximum clock pulse frequency.
Figure 2. The master reset (MR) pulse width, the master reset
to output (Qn) propagation delay and the master reset to clock
removal time.
