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74LV165D-74LV165DB-74LV165PW
8-bit parallel-in/serial-out shift register
1. General descriptionThe 74LV165 is an 8-bit parallel-load or serial-in shift register with complementary serial
outputs (Q7 and Q7) available from the last stage. When the parallel-load input (PL) is
LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously.
When input PL is HIGH, data enters the register serially at the input DS. It shifts one place
to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the
succeeding stage.
The clock input is a gate-OR structure which allows one input to be used as an active
LOW clock enable input (CE) input. The pin assignment for the inputs CP and CE is
arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of the
input CE should only take place while CP HIGH for predictable operation. Either the CP or
the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the
data when PL is activated.
2. Features and benefits Wide supply voltage range from 1.0 Vto 5.5V Synchronous parallel-to-serial applications Optimized for low voltage applications: 1.0 V to 3.6 V Synchronous serial input for easy expansion Latch-up performance exceeds 250 mA 5.5 V tolerant inputs/outputs Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Complies with JEDEC standards: JESD8-5 (2.3 Vto 2.7V) JESD8B/JESD36 (2.7 Vto 3.6V) JESD8-1A (4.5 Vto 5.5V) ESD protection: HBM JESD22-A114-A exceeds 2000V MM JESD22-A115-A exceeds 200V Specified from 40 Cto+85 C and from 40 Cto+125C
74L V165
8-bit parallel-in/serial-out shift register
Rev. 6 — 19 February 2014 Product data sheet
NXP Semiconductors 74LV165
8-bit parallel-in/serial-out shift register
3. Ordering information
4. Functional diagram
Table 1. Ordering information74LV165N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74LV165D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74LV165DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74LV165PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
NXP Semiconductors 74LV165
8-bit parallel-in/serial-out shift registerNXP Semiconductors 74LV165
8-bit parallel-in/serial-out shift register
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 parallel enable input (active LOW) 2 clock input (LOW-to-HIGH edge-triggered) 7 complementary serial output from the last stage
GND 8 ground (0 V) 9 serial output from the last stage 10 serial data input
D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs 15 clock enable input (active LOW)
VCC 16 positive supply voltage
NXP Semiconductors 74LV165
8-bit parallel-in/serial-out shift register
6. Functional description[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Table 3. Function table[1]parallel load L X X X L L L to L L H XXX H H H to H H L
serial shift H L l X L q0 to q5 q6 q6 h X H q0 to q5 q6 q6
hold “do nothing” H H X X X q0 q1 to q6 q7 q7
NXP Semiconductors 74LV165
8-bit parallel-in/serial-out shift register
7. Limiting values[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 12 mW/K above 70C.
[3] Ptot derates linearly with 8 mW/K above 70C.
[4] Ptot derates linearly with 5.5 mW/K above 60C.
8. Recommended operating conditions
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V)[1]
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5V - 20 mA input voltage 0.5 +7 V
IOK output clamping current VO >VCC or VO < 0 - 50 mA output current 0.5 V
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125C
DIP16 package [2]- 750 mW
SO16 package [3]- 500 mW
(T)SSOP16 package [4]- 400 mW
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0V)
VCC supply voltage 1.0 3.3 5.5 V input voltage 0 - VCC V output voltage 0 - VCC V
Tamb ambient temperature 40 - +85 C
t/V input transition rise and fall rate VCC = 1.0 V to 2.0 V 0 - 500 ns/V
VCC = 2.0 V to 2.7 V 0 - 200 ns/V
VCC = 2.7 V to 3.6 V 0 - 100 ns/V
VCC = 3.6 V to 5.5 V 0 - 50 ns/V
NXP Semiconductors 74LV165
8-bit parallel-in/serial-out shift register
9. Static characteristics
[1] Typical values are measured at Tamb = 25C.
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
VIH HIGH-level
input voltage
VCC = 1.2V 0.9 - - 0.9 - V
VCC = 2.3 V to 2.7V 1.4 - - 1.4 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC -V
VIL LOW-level
input voltage
VCC = 1.2V - - 0.3 - 0.3 V
VCC = 2.3 V to 2.7V - - 0.6 - 0.6 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3VCC -0.3VCC
VOH HIGH-level
output voltage
VI = VIH or VIL; IO = 100A
VCC = 1.2V - 1.2 -
VCC = 2.0V 1.8 2.0 - 1.8 - V
VCC = 2.7V 2.5 2.7 - 2.5 - V
VCC = 3.0V 2.8 3.0 - 2.8 - V
VCC = 4.5V 4.3 4.5 - 4.3 - V
standard outputs: VI = VIH or VIL
VCC = 3.0 V; IO = 6 mA 2.40 2.82 - 2.20 - V
VCC = 4.5 V; IO = 12 mA 3.60 4.20 - 3.50 - V
VOL LOW-level
output voltage
VI = VIH or VIL; IO = 100A
VCC = 1.2V - 0 ---
VCC = 2.0V - 0 0.2 1.8 0.2 V
VCC = 2.7V - 0 0.2 2.5 0.2 V
VCC = 3.0V - 0 0.2 2.8 0.2 V
VCC = 4.5V - 0 0.2 4.3 0.2 V
standard outputs: VI = VIH or VIL
VCC = 3.0 V; IO = 6 mA - 0.25 0.40 - 0.50 V
VCC = 4.5 V; IO = 12 mA - 0.35 0.55 - 0.65 V input leakage
current
VI = VCC or GND; VCC =5.5V - - 1- 1 A
ICC supply current VI = VCC or GND; IO =0A;
VCC =5.5V - 20 - 160 A
ICC additional
supply current
VI = VCC – 0.6 V;
VCC= 2.7Vto 3.6V 500 - 850 A input
capacitance
-3.5 - pF
NXP Semiconductors 74LV165
8-bit parallel-in/serial-out shift register
10. Dynamic characteristicsTable 7. Dynamic characteristics
GND (ground = 0 V); for test circuit, see Figure12
tpd propagation
delay
CE, CP to Q7, Q7;
see Figure7 and Figure8
[2]
VCC = 1.2 V - 115 - - - ns
VCC = 2.0V - 38 61 - 76 ns
VCC = 2.7 V - 27 43 - 54 ns
VCC = 3.0 V to 3.6 V [3] -22 36 - 45 ns
VCC = 3.3 V; CL = 15 pF - 18 - - - ns
VCC = 4.5 V to 5.5 V [4] -15 24 - 30 ns
PL to Q7, Q7; see Figure8
VCC = 1.2 V - 110 - - - ns
VCC = 2.0V - 35 56 - 70 ns
VCC = 2.7 V - 24 39 - 49 ns
VCC = 3.0 V to 3.6 V [3] -20 33 - 41 ns
VCC = 3.3 V; CL = 15 pF - 18 - - - ns
VCC = 4.5 V to 5.5 V [4] -14 22 - 27 ns
D7 to Q7, Q7; CL = 15 pF;
see Figure9
VCC = 1.2 V - 90 - - - ns
VCC = 2.0V - 28 45 - 56 ns
VCC = 2.7 V - 20 32 - 40 ns
VCC = 3.0 V to 3.6 V [3] -17 27 - 33 ns
VCC = 3.3 V; CL = 15 pF - 14 - - - ns
VCC = 4.5 V to 5.5 V [4] -11 18 - 22 ns pulse width CP input HIGHto LOW;
see Figure7
VCC = 2.0V 34 10 - 41 - ns
VCC = 2.7 V 25 8 - 30 - ns
VCC = 3.0 V to 3.6 V [3] 20 7 - 24 - ns
VCC = 4.5 V to 5.5 V [4] 15 5 - 18 - ns
PL input LOW; see Figure8
VCC = 2.0V 34 10 - 41 - ns
VCC = 2.7 V 25 8 - 30 - ns
VCC = 3.0 V to 3.6 V [3] 20 7 - 24 - ns
VCC = 4.5 V to 5.5 V [4] 15 5 - 18 - ns
NXP Semiconductors 74LV165
8-bit parallel-in/serial-out shift register
trec recovery time PL to CP, CE; see Figure8
VCC = 1.2 V - 40 - - - ns
VCC = 2.0V 24 15 - 30 - ns
VCC = 2.7 V 18 11 - 23 - ns
VCC = 3.0 V to 3.6 V [3] 17 10 - 21 - ns
VCC = 4.5 V to 5.5 V [4] 12 7 - 15 - ns
tsu set-up time DS to CP , CE; see Figure10
VCC = 1.2 V - 8- - - ns
VCC = 2.0V 22 2- 26 - ns
VCC = 2.7 V 16 1- 19 - ns
VCC = 3.0 V to 3.6 V [3] 13 1- 15 - ns
VCC = 4.5 V to 5.5 V [4] 90 - 10 - ns
CE to CP , CP to CE;
see Figure10
VCC = 1.2 V - 20 - - - ns
VCC = 2.0V 22 7 - 26 - ns
VCC = 2.7 V 16 5 - 19 - ns
VCC = 3.0 V to 3.6 V [3] 13 4 - 15 - ns
VCC = 4.5 V to 5.5 V [4] 93 - 10 - ns
Dn to PL;
see Figure11
VCC = 1.2 V - 25 - - - ns
VCC = 2.0V 22 8 - 26 - ns
VCC = 2.7 V 16 6 - 19 - ns
VCC = 3.0 V to 3.6 V [3] 13 5 - 15 - ns
VCC = 4.5 V to 5.5 V [4] 94 - 10 - ns hold time DS to CP , CE; Dn to PL;
see Figure10 and Figure11
VCC = 1.2 V - 20 - - - ns
VCC = 2.0V 22 7 - 26 - ns
VCC = 2.7 V 16 5 - 19 - ns
VCC = 3.0 V to 3.6 V [3] 13 4 - 15 - ns
VCC = 4.5 V to 5.5 V [4] 93 - 10 - ns
CE to CP , CP to CE;
see Figure10
VCC = 1.2 V - 30 - - - ns
VCC = 2.0V 5 8- 5 - ns
VCC = 2.7 V 5 6- 5 - ns
VCC = 3.0 V to 3.6 V [3] 5 5- 5 - ns
VCC = 4.5 V to 5.5 V [4] 5 4- 5 - ns
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); for test circuit, see Figure12
NXP Semiconductors 74LV165
8-bit parallel-in/serial-out shift register
[1] Typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPHL and tPLH.
[3] Typical values are measured at VCC = 3.3 V.
[4] Typical values are measured at VCC = 5.0 V.
[5] CPD is used to determine the dynamic power dissipation PD = CPD VCC 2 fi + (CL VCC 2 fo) (PD in W), where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC 2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
11. Waveforms
fmax maximum
frequency
see Figure7
VCC = 2.0V 14 40 - 12 - MHz
VCC = 2.7 V 19 60 - 16 - MHz
VCC = 3.0 V to 3.6 V [3] 24 65 - 20 - MHz
VCC = 3.3 V; CL = 15 pF - 78 - - - MHz
VCC = 4.5 V to 5.5 V [4] 36 75 - 30 - MHz
CPD power
dissipation
capacitance =GNDto VCC; VCC = 3.3 V [5] -35 - pF
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); for test circuit, see Figure12
NXP Semiconductors 74LV165
8-bit parallel-in/serial-out shift register
