74LV125PW ,Quad buffer/line driver; 3-stateFEATURES DESCRIPTIONThe 74LV125 is a low-voltage Si-gate CMOS device and is pin and• Wide operating ..
74LV125PW ,Quad buffer/line driver; 3-stateapplications: 1.0 to 3.6 VThe 74LV125 consists of four non-inverting buffers/line drivers with• Acc ..
74LV125PW ,Quad buffer/line driver; 3-stateapplications: 1.0 V to 3.6 Vn Accepts TTL input levels between V = 2.7 V and V = 3.6 VCC CCn Typica ..
74LV125PW ,Quad buffer/line driver; 3-stateapplications: 1.0 to 3.6 VThe 74LV125 consists of four non-inverting buffers/line drivers with• Acc ..
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74LV132 ,Quad 2-input NAND Schmitt-trigger
7MBI40N-120 ,IGBT(1200V/40A)IGBT MODULE ( N series )n n n n Outline Drawing• • • • • • Overcurrent Limiting Function( 4 ~ 5 Tim ..
7MBP100RA060 ,Intelligent Power Module
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74LV125D-74LV125DB-74LV125N-74LV125PW
Quad buffer/line driver 3-State
Product specification
Supersedes data of 1997 Feb 03
IC24 Data Handbook
1998 Apr 28
Philips Semiconductors Product specification
74LV125Quad buffer/line driver (3-State)
FEATURES Wide operating voltage: 1.0 to 5.5 V Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C. Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25°C. Output capability: bus driver ICC category: MSI
DESCRIPTIONThe 74LV125 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT125.
The 74LV125 consists of four non-inverting buffers/line drivers with
3-state outputs. The 3-state outputs (nY) are controlled by the output
enable input (nOE). A HIGH at nOE causes the outputs to assume a
high impedance OFF-state.
QUICK REFERENCE DATAGND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
NOTE: CPD is used to determine the dynamic power dissipation (PD in μW)
PD = CPD × VCC 2 × fi (CL × VCC 2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of the outputs.
ORDERING INFORMATION
PIN DESCRIPTION
FUNCTION TABLE
NOTES:H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
Philips Semiconductors Product specification
74LV125Quad buffer/line driver (3-State)
PIN CONFIGURATION
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
RECOMMENDED OPERATING CONDITIONS
NOTE: The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
Philips Semiconductors Product specification
74LV125Quad buffer/line driver (3-State)
ABSOLUTE MAXIMUM RATINGS1, 2In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICSOver recommended operating conditions, voltages are referenced to GND (ground = 0 V)
Philips Semiconductors Product specification
74LV125Quad buffer/line driver (3-State)
DC ELECTRICAL CHARACTERISTICS (Continued)Over recommended operating conditions, voltages are referenced to GND (ground = 0 V)
NOTE: All typical values are measured at Tamb = 25°C.
AC CHARACTERISTICSGND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
NOTES: Unless otherwise stated, all typical values are measured at Tamb = 25°C Typical values are measured at VCC = 3.3 V.
Philips Semiconductors Product specification
74LV125Quad buffer/line driver (3-State)
AC WAVEFORMSVM = 1.5 V at VCC ≥ 2.7 V and ≤ 3.6 V;
VM = 0.5 × VCC at VCC < 2.7 V and ≥ 4.5 V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
VX = VOL + 0.3 V at VCC ≥ 2.7 V and ≤ 3.6 V;
VX = VOL + 0.1 × VCC at VCC < 2.7 V and ≥ 4.5 V.
VY = VOH – 0.3 V at VCC ≥ 2.7 V and ≤ 3.6 V;
VY = VOH – 0.1 ⋅ VCC at VCC < 2.7 V and ≥ 4.5 V.
Figure 1. Input (nA) to output (nY) propagation delays
and output transition times.
Figure 2. 3-state enable and disable times.
TEST CIRCUIT
Figure 3. Load circuitry for switching times.
