74LV08D ,Quad 2-input AND gateLogic diagram (one gate)5. Pinning information5.1 Pinning74LV0874LV081 141A VCC1B 2 13 4B1A 1 14 VC ..
74LV08D ,Quad 2-input AND gateapplications: 1.0 to 3.6 VThe 74LV08 provides the 2-input AND function.• Accepts TTL input levels b ..
74LV08D ,Quad 2-input AND gateapplications: 1.0 to 3.6 VThe 74LV08 provides the 2-input AND function.• Accepts TTL input levels b ..
74LV08N ,Quad 2-input AND gateFEATURES DESCRIPTIONThe 74LV08 is a low-voltage Si-gate CMOS device and is pin and• Wide operating ..
74LV08PW ,Quad 2-input AND gatePIN CONFIGURATION LOGIC SYMBOL1A1A 1 14 1VCC 1Y31B21B 2 13 4B2A42Y1Y 3 12 4A62B52A 4 11 4Y3A93Y83B2 ..
74LV08PW ,Quad 2-input AND gateINTEGRATED CIRCUITS74LV08Quad 2-input AND gateProduct specification 1998 Apr 20Supersedes data of 1 ..
7MBI40N-120 ,IGBT(1200V/40A)IGBT MODULE ( N series )n n n n Outline Drawing• • • • • • Overcurrent Limiting Function( 4 ~ 5 Tim ..
7MBP100RA060 ,Intelligent Power Module
7MBP100RA120 ,IGBT-IPM(1200V/100A)
7MBP150RA060 ,Intelligent Power Module
7MBP150RA120 ,IGBT-IPM(1200V/150A)
7MBP25RA120 ,IGBT-IPM(1200V/25A)
74LV08D-74LV08N-74LV08PW
Quad 2-input AND gate
Product specification
Supersedes data of 1997 Feb 03
IC24 Data Handbook
1998 Apr 20
Philips Semiconductors Product specification
74LV08Quad 2-input AND gate
FEATURES Wide operating voltage: 1.0 to 5.5 V Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C. Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25°C. Output capability: standard ICC category: SSI
DESCRIPTIONThe 74LV08 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT08.
The 74LV08 provides the 2-input AND function.
QUICK REFERENCE DATAGND = 0 V; Tamb = 25°C; tr = tf 2.5 ns
NOTES: CPD is used to determine the dynamic power dissipation (PD in μW)
PD = CPD VCC2 fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL VCC 2 fo) = sum of the outputs. The condition is VI = GND to VCC.
ORDERING INFORMATION
PIN DESCRIPTION
FUNCTION TABLE
NOTES:H = HIGH voltage level
L = LOW voltage level
Philips Semiconductors Product specification
74LV08Quad 2-input AND gate
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
LOGIC SYMBOL
LOGIC DIAGRAM (ONE GATE)
RECOMMENDED OPERATING CONDITIONS
NOTE: The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
Philips Semiconductors Product specification
74LV08Quad 2-input AND gate
ABSOLUTE MAXIMUM RATINGS1, 2In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICSOver recommended operating conditions. Voltages are referenced to GND (ground = 0V).
Philips Semiconductors Product specification
74LV08Quad 2-input AND gate
DC ELECTRICAL CHARACTERISTICS (Continued)Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
NOTE: All typical values are measured at Tamb = 25°C.
AC CHARACTERISTICSGND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
NOTES: Unless otherwise stated, all typical values are measured at Tamb = 25°C. Typical values are measured at VCC = 3.3 V.
AC WAVEFORMSVM = 1.5 V at VCC ≥ 2.7 V and ≤ 3.6 V;
VM = 0.5 × VCC at VCC < 2.7 V and ≥ 4.5 V;
VOL and VOH are the typical output voltage drop that occur with the
output load.
Figure 1. Input (nA, nB) to output (nY) propagation delays
and output transition times.
TEST CIRCUIT
Figure 2. Load circuitry for switching times.
Philips Semiconductors Product specification
74LV08Quad 2-input AND gate
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
