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74LV03D
Quad 2-input NAND gate
Product specification
Supersedes data of 1997 Mar 28
IC24 Data Handbook
1998 Apr 20
Philips Semiconductors Product specification
74LV03Quad 2-input NAND gate
FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V,
Tamb = 25°C Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V,
Tamb = 25°C Level shifter capability Output capability: standard (open drain) ICC category: SSI
DESCRIPTIONThe 74LV03 is a low–voltage Si–gate CMOS device and is pin and
function compatible with 74HC/HCT03.
The 74LV03 provides the 2–input NAND function.
The 74LV03 has open–drain N–transistor outputs, which are not
clamped by a diode connected to VCC. In the OFF–state, i.e. when
one input is LOW, the output may be pulled to any voltage between
GND and VOmax. This allows the device to be used as a
LOW–to–HIGH or HIGH–to–LOW level shifter. For digital operation
and OR–tied output applications, these devices must have a pull–up
resistor to establish a logic HIGH level.
QUICK REFERENCE DATAGND = 0V; Tamb = 25°C; tr =tf 2.5 ns
NOTES:1CPD is used to determine the dynamic power dissipation (PD in μW)
PD = CPD VCC 2 x fi (CL VCC 2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL VCC 2 fo) = sum of the outputs. The condition is VI = GND to VCC The given value of CPD is obtained with : CL = 0 pF and RL = ∞
ORDERING INFORMATION
PIN DESCRIPTION
FUNCTION TABLE
NOTES:H = HIGH voltage level
L = LOW voltage level
Z = High impedance OFF-state
Philips Semiconductors Product specification
74LV03Quad 2-input NAND gate
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
LOGIC SYMBOL
LOGIC DIAGRAM
Philips Semiconductors Product specification
74LV03Quad 2-input NAND gate
RECOMMENDED OPERATING CONDITIONS
NOTES: The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
ABSOLUTE MAXIMUM RATINGS1, 2In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors Product specification
74LV03Quad 2-input NAND gate
DC CHARACTERISTICSOver recommended operating conditions voltages are referenced to GND (ground = 0V)
NOTES: All typical values are measured at Tamb = 25°C. The maximum operating output voltage (VO(max)) is 6.0V.
Philips Semiconductors Product specification
74LV03Quad 2-input NAND gate
AC CHARACTERISTICS FOR 74LV03GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
NOTE: Unless otherwise stated, all typical values are at Tamb = 25°C. Typical value measured at VCC = 3.3V. Typical value measured at VCC = 5.0V.
AC WAVEFORMSVM = 1.5V at VCC � 2.7V � 3.6V
VM = 0.5V * VCC at VCC � 2.7V and � 4.5V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VX = VOL + 0.3V at VCC � 2.7V and � 3.6V
VX = VOL + 0.1 * VCC at VCC � 2.7V and � 4.5V
Figure 1. Input (nA, nB) to output (nY) propagation delays.
TEST CIRCUIT
Figure 2. Load circuitry for switching times
