74LV02D Fast Delivery |IC PHOENIX CO.,LIMITED

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74LV02D
Quad 2-input NOR gate
General descriptionThe 74LV02isa low-voltage Si-gate CMOS device thatis pin and function compatible with
74HC02 and 74HCT02.
The 74LV02 provides a quad 2-input NOR function. Features Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25°C Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb =25°C ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V Multiple package options Speciﬁed from −40 °Cto+85 °C and from −40°Cto +125°C Ordering information
74L V02
Quad 2-input NOR gate
Rev. 04 — 20 December 2007 Product data sheet
Table 1. Ordering information
74LV02D −40°Cto +125°C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LV02PW −40°Cto +125°C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LV02BQ −40°Cto +125°C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad ﬂat package; no leads; 14 terminals;
body 2.5×3× 0.85 mm
SOT762-1
NXP Semiconductors 74L V02
Quad 2-input NOR gate Functional diagram Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 data output 2 data input 3 data input
NXP Semiconductors 74L V02
Quad 2-input NOR gate Functional description Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70°C.
[3] Ptot derates linearly with 5.5 mW/K above 60°C.
[4] Ptot derates linearly with 4.5 mW/K above 60°C. 4 data output 5 data input 6 data input
GND 7 ground (0 V) 8 data input 9 data input 10 data output 11 data input 12 data input 13 data output
VCC 14 supply voltage
Table 2. Pin description …continued
Table 3. Function table= HIGH voltage level; L= LOW voltage level; X= don’t care
LLH L L
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5 V orVI >VCC+ 0.5V [1]- ±20 mA
IOK output clamping current VO< −0.5 V orVO >VCC+ 0.5V [1]- ±50 mA output current VO = −0.5 V to (VCC+ 0.5V) - ±25 mA
ICC supply current - 50 mA
IGND ground current −50 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125°C
SO14 package [2]- 500 mW
TSSOP14 package [3]- 500 mW
DHVQFN14 package [4]- 500 mW
NXP Semiconductors 74L V02
Quad 2-input NOR gate Recommended operating conditions
[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC=1.0 V (with input levels GND or VCC). Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
VCC supply voltage [1] 1.0 3.3 5.5 V input voltage 0 - VCC V output voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V
VCC = 2.0 V to 2.7 V - - 200 ns/V
VCC = 2.7 V to 3.6 V - - 100 ns/V
VCC = 3.6 V to 5.5 V - - 50 ns/V
Table 6. Static characteristics
Voltages are referenced to GND (ground = 0 V).
VIH HIGH-level input voltage VCC = 1.2 V 0.9 - - 0.9 - V
VCC = 2.0 V 1.4 - - 1.4 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V to 5.5 V 0.7VC - 0.7VCC -V
VIL LOW-level input voltage VCC = 1.2 V - - 0.3 - 0.3 V
VCC = 2.0 V - - 0.6 - 0.6 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCCV
VOH HIGH-level output voltage VI = VIH or VIL
IO = −100 μA; VCC = 1.2V - 1.2 - - - V
IO = −100 μA; VCC = 2.0V 1.8 2.0 - 1.8 - V
IO = −100 μA; VCC = 2.7V 2.5 2.7 - 2.5 - V
IO = −100 μA; VCC = 3.0V 2.8 3.0 - 2.8 - V
IO = −100 μA; VCC = 4.5V 4.3 4.5 - 4.3 - V
IO = −6 mA; VCC = 3.0V 2.4 2.82 - 2.2 - V
IO = −12 mA; VCC = 4.5V 3.6 4.2 - 3.5 - V
NXP Semiconductors 74L V02
Quad 2-input NOR gate
[1] Typical values are measured at Tamb = 25°C.
10. Dynamic characteristics
[1] All typical values are measured at Tamb =25°C.
[2] tpd is the same as tPLH and tPHL.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0V).
[4] CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where: = input frequency in MHz, fo= output frequency in MHz= output load capacitance inpF
VCC= supply voltage in V= number of inputs switching
Σ(CL× VCC2×fo)= sum of the outputs.
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 μA; VCC = 1.2V - 0 - - - V
IO = 100 μA; VCC = 2.0V - 0 0.2 - 0.2 V
IO = 100 μA; VCC = 2.7V - 0 0.2 - 0.2 V
IO = 100 μA; VCC = 3.0V - 0 0.2 - 0.2 V
IO = 100 μA; VCC = 4.5V - 0 0.2 - 0.2 V
IO = 6 mA; VCC = 3.0V - 0.25 0.40 - 0.50 V
IO = 12 mA; VCC = 4.5V - 0.35 0.55 - 0.65 V input leakage current VI =VCCor GND; VCC= 5.5V - - 1.0 - 1.0 μA
ICC supply current VI = VCC or GND; IO = 0A;
VCC= 5.5V - 20.0 - 40 μA
ΔICC additional supply current per input; VI = VCC − 0.6V;
VCC= 2.7Vto 3.6V - 500 - 850 μA input capacitance - 3.5 - - - pF
Table 6. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristics
GND = 0 V; For test circuit see Figure7.
tpd propagation delay nA, nBto nY; see Figure6 [2]
VCC = 1.2 V - 40 - - - ns
VCC = 2.0 V - 14 21 - 26 ns
VCC = 2.7 V - 10 15 - 19 ns
VCC = 3.0 V to 3.6 V; CL =15pF [3] - 6.0 - - - ns
VCC = 3.0 V to 3.6 V [3] - 7.5 12 - 15 ns
VCC = 4.5 V to 5.5 V [3] - 6.0 10 - 13 ns
CPD power dissipation
capacitance=50 pF; fi = 1 MHz;= GNDto VCC
[4] -22 - - - pF
NXP Semiconductors 74L V02
Quad 2-input NOR gate
11. Waveforms
Table 8. Measurement points
< 2.7 V 0.5VCC 0.5VCC
2.7 V to 3.6V 1.5 V 1.5 V
≥ 4.5 V 0.5VCC 0.5VCC
Table 9. Test data
< 2.7 V VCC ≤ 2.5 ns
2.7 V to 3.6V 2.7 V ≤ 2.5 ns
≥ 4.5 V VCC ≤ 2.5 ns

Partno	Mfg	Dc	Qty	Available	Descript
74LV02D	NXP	N/a	868	avai	Quad 2-input NOR gate