SN54LS95J ,4-BIT SHIFT REGISTERSN54/74LS95B4-BIT SHIFT REGISTERThe SN54/74LS95B is a 4-Bit Shift Register with serial and parallel ..
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SN54S03J ,Quadruple 2-Input Positive-NAND Gates With Open-Collector OutputSM5403, SN54LSU3, su54333,SDLS028 su7403. SN74L803, sn74suanUADRUPLE 2-INPUT P08lTl1lE-tlAN0 GATES ..
SN54S03J ,Quadruple 2-Input Positive-NAND Gates With Open-Collector Outputmaximum ratings over operating free-air temperature range (unless otherwise noted).nReseuor vatues ..
SN74HC14DRG4 ,Hex Schmitt-Trigger Inverters 14-SOIC -40 to 85Maximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74HC14N ,Hex Schmitt-Trigger InvertersFeatures list 1• Added Pin Configuration and Functions section, ESD Ratings table, Feature Descript ..
SN74HC14NE4 , HEX SCHMITT-TRIGGER INVERTERS
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SN74HC14PWLE ,Hex Schmitt-Trigger InvertersLogic Diagram (Positive Logic)A Y1An IMPORTANT NOTICE at the end of this data sheet addresses avail ..
74LS95-SN54LS95J-SN74LS95N
4-bit Parallel Access Shift Registers
4-BIT SHIFT REGISTERThe SN54/74LS95B is a 4-Bit Shift Register with serial and parallel
synchronous operating modes. The serial shift right and parallel load are acti-
vated by separate clock inputs which are selected by a mode control input.
The data is transferred from the serial or parallel D inputs to the Q outputs
synchronous with the HIGH to LOW transition of the appropriate clock input.
The LS95B is fabricated with the Schottky barrier diode process for high
speed and is completely compatible with all Motorola TTL families. Synchronous, Expandable Shift Right Synchronous Shift Left Capability Synchronous Parallel Load Separate Shift and Load Clock Inputs Input Clamp Diodes Limit High Speed Termination Effects
NOTE:
The Flatpak version has the
same pinouts (Connection
Diagram) as the Dual In-Line
Package.
CONNECTION DIAGRAM DIP (TOP VIEW)- - - -- -- -- -- -- --- -- -- -- -- --
PIN NAMES LOADING (Note a) Mode Control Input Serial Data Input
P0–P3 Parallel Data Inputs
CP1 Serial Clock (Active LOW Going Edge) Input
CP2 Parallel Clock (Active LOW Going Edge) Input
Q0–Q3 Parallel Outputs (Note b)
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
GUARANTEED OPERATING RANGES
