SN54LS75J ,4-BIT D LATCHSN54/74LS754-BIT D LATCHSN54/74LS77The TTL/MSI SN54/74LS75 and SN54/74LS77 are latches used as tem- ..
SN54LS76J ,DUAL JK FLIP-FLOP WITH SET AND CLEAR
SN54LS795J ,TRI-STATE OCTAL BUFFERS
SN54LS796J ,TRI-STATE OCTAL BUFFERS
SN54LS796J ,TRI-STATE OCTAL BUFFERS
SN54LS797J ,TRI-STATE OCTAL BUFFERS
SN74HC139N ,Dual 2-Line To 4-Line Decoders/Demultiplexersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74HC139NSR ,Dual 2-Line To 4-Line Decoders/Demultiplexers/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74HC139PW ,Dual 2-Line To 4-Line Decoders/Demultiplexerslogic diagram (positive logic)41Y011G 51Y161Y221A73 1Y31B122Y0152G 112Y1102Y2142A92Y3132BPin number ..
SN74HC139PWLE ,Dual 2-Line To 4-Line Decoders/Demultiplexersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HC139PWR ,Dual 2-Line To 4-Line Decoders/Demultiplexers/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74HC139PWR ,Dual 2-Line To 4-Line Decoders/Demultiplexers/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
74LS75-SN54LS75J-SN74LS75N
Quad Latch
NOTES:
tn = bit time before enable
negative-going transition
tn+1 = bit time after enable
4-BIT D LA TCHThe TTL/MSI SN54/74LS75 and SN54/74LS77 are latches used as tem-
porary storage for binary information between processing units and input/out-
put or indicator units. Information present at a data (D) input is transferred to
the Q output when the Enable is HIGH and the Q output will follow the data
input as long as the Enable remains HIGH. When the Enable goes LOW, the
information (that was present at the data input at the time the transition oc-
curred) is retained at the Q output until the Enable is permitted to go HIGH.
The SN54/74LS75 features complementary Q and Q output from a 4-bit
latch and is available in the 16-pin packages. For higher component density
applications the SN54/74LS77 4-bit latch is available in the 14-pin package
with Q outputs omitted.
CONNECTION DIAGRAMS DIP (TOP VIEW) Q1 E0–1 GND Q2Q2 Q3 D1 E2–3 VCC D2 D3 Q3 Q1 E0–1 GND NC Q2 Q3 D1 E2–3 VCC D2 D3 NC
PIN NAMES LOADING (Note a)D1–D4
E0–1
E2–3
Q1–Q4
Q1–Q4
Data Inputs
Enable Input Latches 0, 1
Enable Input Latches 2, 3
Latch Outputs (Note b)
Complimentary Latch Outputs (Note b)
NOTES: 1 Unit Load (U.L.) = 40 μA HIGH. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
TRUTH TABLE
(Each latch)
