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74LS74-DM54LS74AJ
Dual Positive-Edge-Triggered D Flip-Flops with Preset/ Clear and Complementary Outputs
TL/F/6373
54LS74/DM54LS74A/DM74LS74A
Dual
Positive-Edge-Triggered
Flip-Flops
with
Preset,
Clear
and
Complementary
Outputs
June 1989
54LS74/DM54LS74A/DM74LS74A
Dual Positive-Edge-TriggeredD Flip-Flops
with Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
geredD flip-flopswith complementary outputs.The informa-
tionontheD inputis acceptedbythe flip-flopsonthe posi-
tive going edgeof theclock pulse.The triggeringoccursata
voltage levelandisnot directly relatedtothe transition timethe rising edgeofthe clock. The dataontheD input may changed whilethe clockislowor high without affecting
the outputsas longasthe datasetupand hold times arenot
violated.Alow logic levelonthe presetor clear inputswill
setor resetthe outputs regardlessofthe logic levelsofthe
other inputs.
Features Alternate military/aerospace device (54LS74)is avail-
able. Contacta National Semiconductor Sales Office/
Distributorfor specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6373–1
Order Number 54LS74DMQB, 54LS74FMQB,54LS74LMQB,
DM54LS74AJ, DM54LS74AW,DM74LS74AMor DM74LS74AN
See NSPackage Number E20A, J14A, M14A, N14A orW14B
Function Table
Inputs Outputs CLR CLK D Q Q X X H L X X L H X X H* H* u HH L u LL H L X Q0 Q0eHigh Logic Levele EitherLow orHighLogicLeveleLow Logic Levele Positive-goingTransitionThis configurationis nonstable; thatis,itwillnotpersistwheneitherthe preset
and/or clearinputs returntotheir inactive (high) level.eThe outputlogiclevel ofQbeforethe indicatedinput conditionswere established.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
