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Partno	Mfg	Dc	Qty	Available	Descript
74LS640	MIT	N/a	50	avai	OCTAL BUS TRANSCEIVERS

74LS640 ,OCTAL BUS TRANSCEIVERS
74LS641 ,Octal Bus Transceiver
74LS641 ,Octal Bus Transceiver
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74LS640
OCTAL BUS TRANSCEIVERS
CONNECTION DIAGRAMS DIP (TOP VIEW)
VCC
DIR B2 B3 B5B4 B6 A2 A3 A4 A5 A6 A7 GND B8
VCC
DIR B2 B3 B5B4 B6 A2 A3 A4 A5 A6 A7 GND B8
SN54/74LS640
SN54/74LS642
SN54/74LS641
SN54/74LS645
ENABLE
ENABLE
OCT AL BUS TRANSCEIVERS
These octal bus transceivers are designed for asynchronous two-way
communication between data buses. Control function implementation
minimizes external timing requirements. These circuits allow data transmis-
sion from the A bus to B or from the B bus to A bus depending upon the logic
level of the direction control (DIR) input. Enable input (G) can disable the
device so that the buses are effectively isolated.
DEVICE OUTPUT LOGIC
LS640 3-State Inverting
LS641 Open-Collector True
LS642 Open-Collector Inverting
LS645 3-State True
FUNCTION TABLE
H = HIGH Level, L = LOW Level, X = Irrelevant

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