74LS390 ,Dual 4-Bit Decade CounterDM74LS390 Dual 4-Bit Decade CounterAugust 1986Revised March 2000DM74LS390Dual 4-Bit Decade Counter
74LS390 ,Dual 4-Bit Decade CounterFeaturesEach of these monolithic circuits contains eight master- Dual version of the popular DM74L ..
74LS393 ,Dual 4-Bit Binary CounterLOGIC DIAGRAM (one half shown)* ** * * ** * * ** * * * * * ** * * ** * ** * * ** * * *SN54/74LS393
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79RV4640-180DU , Low-Cost Embedded 64-bit RISController w/ DSP Capability
7B33-01-2 ,Isolated Voltage Input Signal Conditioning Module -100 Hz Bandwidthapplications protection. The power supplies necessary to drive each of the including process contro ..
7B34-01-2 ,Isolated 2 or 3-Wire RTD Input Signal Conditioning Moduleapplications protection. The power supplies necessary to drive each of the including process contro ..
7B34-02-2 ,Isolated 2 or 3-Wire RTD Input Signal Conditioning Modulefeatures a nonlinearity of +0.05% maximum (Pt RTDs). To accurately measure low level signals in el ..
7B35-01-2 ,Isolated Process Current Input Signal Conditioning Module with Isolated 24 V Loop Powerapplications protection. The power supplies necessary to drive each of the including process contro ..
7B37-J-01-2 ,Isolated Thermocouple Input Signal Conditioning ModuleAPPLICATIONS Industrial signal conditioning Figure 1. 7B37 Functional Block Diagram Industrial sig ..
74LS390
Dual 4-Bit Decade Counter
DM74LS390 Dual 4-Bit Decade Counter August 1986 Revised March 2000 DM74LS390 Dual 4-Bit Decade Counter General Description Features Each of these monolithic circuits contains eight master- � Dual version of the popular DM74LS90 slave flip-flops and additional gating to implement two indi- � DM74LS390...individual clocks for A and B flip-flops vidual four-bit counters in a single package. The provide dual ÷ 2 and ÷ 5 counters DM74LS390 incorporates dual divide-by-two and divide- � Direct clear for each 4-bit counter by-five counters, which can be used to implement cycle � Dual 4-bit version can significantly improve system den- lengths equal to any whole and/or cumulative multiples of 2 sities by reducing counter package count by 50% and/or 5 up to divide-by-100. When connected as a bi-qui- nary counter, the separate divide-by-two circuit can be � Typical maximum count frequency...35 MHz used to provide symmetry (a square wave) at the final out- � Buffered outputs reduce possibility of collector commu- put stage. The DM74LS390 has parallel outputs from each tation counter stage so that any submultiple of the input count fre- quency is available for system-timing signals. Ordering Code: Order Number Package Number Package Description DM74LS390M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS390N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 DS006433
