74LS37 ,3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-FlopsDM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-FlopsApril 1 ..
74LS373 ,3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-FlopsGeneral Description
These 8-bit registers feature totem-pole 3-STATE outputs
designed specifica ..
74LS374 ,3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-FlopsFeaturesThese 8-bit registers feature totem-pole 3-STATE outputs Choice of 8 latches or 8 D-type f ..
74LS377 ,Octal D-Type Flip-Flop with Common Enable and ClockFunctional DescriptionThe DM74LS377 consists of eight edge-triggered D flip-flops with individual D ..
74LS377 ,Octal D-Type Flip-Flop with Common Enable and ClockFeaturesThe DM74LS377 is an 8-bit register built using advanced 8-bit high speed parallel register ..
74LS377 ,Octal D-Type Flip-Flop with Common Enable and Clockfeatures the common Enablerather then common Master Reset.J SUFFIX• 8-Bit High Speed Parallel Regis ..
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79L15 , TO-92 Plastic-Encapsulate Transistors
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74LS37-74LS374
3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops April 1986 Revised March 2000 DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description Features These 8-bit registers feature totem-pole 3-STATE outputs � Choice of 8 latches or 8 D-type flip-flops in a single designed specifically for driving highly-capacitive or rela- package tively low-impedance loads. The high-impedance state and � 3-STATE bus-driving outputs increased high-logic level drive provide these registers with � Full parallel-access for loading the capability of being connected directly to and driving the � Buffered control inputs bus lines in a bus-organized system without need for inter- � P-N-P inputs reduce D-C loading on data lines face or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the DM74LS373 are transparent D- type latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. The eight flip-flops of the DM74LS374 are edge-triggered D-type flip flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-imped- ance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF. Ordering Code: Order Number Package Number Package Description DM74LS373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74LS374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide IDM29901NC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 DS006431
