74LS257 ,3-STATE Quad 2-Data Selectors/MultiplexersFeaturesdata lines of bus-organized systems. With all but one of thecommon outputs disabled (at a h ..
74LS259 ,8-Bit Addressable Latchesapplicationsling the clear and enable inputs as enumerated in the func- Four distinct functional mo ..
74LS266 ,Quad 2-Input Exclusive-NOR Gate with Open-Collector OutputsGeneral DescriptionThis device contains four independent gates each of whichperforms the logic excl ..
74LS273 ,8-Bit Register with ClearSN54/74LS273OCTAL D FLIP-FLOP WITH CLEARThe SN54/ 74LS273 is a high-speed 8-Bit Register. The regis ..
74LS279 ,Quad S-R LatchGeneral DescriptionThe DM74LS279 consists of four individual and indepen-dent Set-Reset Latches wit ..
74LS279 ,Quad S-R LatchDM74LS279 Quad S-R LatchAugust 1986Revised March 2000DM74LS279Quad S-R Latch
790D ,Resin-Molded, Radial-Lead Solid Tantalum CapacitorsDocument Number 42072 , contact europetantalum115Revision 26-Mar-02790DResin-Coated, Radial-LeadedV ..
7914J-1-000 , BOURNS OFFERS OVER 35 ASSORTED KITS
7914J-1-000 , BOURNS OFFERS OVER 35 ASSORTED KITS
7914J-1-024E , 4 mm SMD & Through-hole Sealed Key Switch
79L05ACZ , Three-Terminal Low Current Negative Voltage Regulators
79L06 , TO-92 Plastic-Encapsulate Transistors
74LS257
3-STATE Quad 2-Data Selectors/Multiplexers
DM74LS257B 3-STATE Quad 2-Data Selectors/Multiplexers June 1989 Revised November 1999 DM74LS257B 3-STATE Quad 2-Data Selectors/Multiplexers for data buses. It also permits the use of standard TTL reg- General Description isters for data retention throughout the system. These Schottky-clamped high-performance multiplexers feature 3-STATE outputs that can interface directly with Features data lines of bus-organized systems. With all but one of the common outputs disabled (at a high impedance state), the3-STATE versions LS157 and LS158 with same pinouts low impedance of the single enabled output will drive theSchottky-clamped for significant improvement in A-C bus line to a HIGH or LOW logic level. To minimize the pos- performance sibility that two outputs will attempt to take a common bus Provides bus interface from multiple sources in to opposite logic levels, the output enable circuitry is high-performance systems designed such that the output disable times are shorter Average propagation delay from data input 12 ns than the output enable times. Typical power dissipation: 50 mW This 3-STATE output feature means that n-bit (paralleled) data selectors with up to 258 sources can be implemented Ordering Code: Order Number Package Number Package Description DM74LS257BM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS257BN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Diagram Function Table Inputs Output Y Output Select A B LS257 Control HX X X Z LL L X L LL H X H LH X L L LH X H H H = HIGH Level X = Don’t Care L = LOW Level Z = High Impedance (off) © 1999 DS006417
