74LS244 ,Octal 3-STATE Buffer/Line Driver/Line ReceiverFeaturesThese buffers/line drivers are designed to improve both the 3-STATE outputs drive bus line ..
74LS245 ,3-STATE Octal Bus TransceiverFeaturesThese octal bus transceivers are designed for asynchro- Bi-Directional bus transceiver in ..
74LS247 ,8CD-to-Seven-Segment Decoders/Drivers(with 15V outputs)3SN74LS247LS247FUNCTION TABLEDECIMALINPUTS OUTPUTSOR OR BI/RBO BI/RBO NOTE NOTEFUNCTIONLT RBI D C B ..
74LS249 , BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
74LS249 , BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
74LS249 , BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
78Q2123 ,10/100 Fast Ethernet MicroPHYPin Description.......11 2.1 Legend...11 2.2 MII (Media Independent Interface) ....11 2.3 Control a ..
78Q2123/F ,10/100 Fast Ethernet MicroPHYapplications. The MDI isnegotiation and 10BASE-T signal receptionconnected to the line media via du ..
78SR105HC , 1.5 AMP POSITIVE STEP-DOWN INTEGRATED SWITCHING REGULATOR
78SR112SC , 1.5 AMP POSITIVE STEP-DOWN INTEGRATED SWITCHING REGULATOR
78SR112SC , 1.5 AMP POSITIVE STEP-DOWN INTEGRATED SWITCHING REGULATOR
78SR112SC , 1.5 AMP POSITIVE STEP-DOWN INTEGRATED SWITCHING REGULATOR
74LS244
Octal 3-STATE Buffer/Line Driver/Line Receiver
DM74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver August 1986 Revised March 2000 DM74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver General Description Features These buffers/line drivers are designed to improve both the � 3-STATE outputs drive bus lines directly performance and PC board density of 3-STATE buffers/ � PNP inputs reduce DC loading on bus lines drivers employed as memory-address drivers, clock driv- � Hysteresis at data inputs improves noise margins ers, and bus-oriented transmitters/receivers. Featuring 400 � Typical I (sink current) 24 mA OL mV of hysteresis at each low current PNP data line input, they provide improved noise rejection and high fanout out- � Typical I (source current) −15 mA OH puts and can be used to drive terminated lines down to � Typical propagation delay times 133Ω. Inverting 10.5 ns Noninverting 12 ns � Typical enable/disable time 18 ns � Typical power dissipation (enabled) Inverting 130 mW Noninverting 135 mW Ordering Code: Order Number Package Number Package Description DM74LS244WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS244N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Output G AY LLL LH H HX Z L = LOW Logic Level H = HIGH Logic Level X = Either LOW or HIGH Logic Level Z = High Impedance © 2000 DS008442
