74LS221N ,DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS2SN74LS221OPERATIONAL NOTESOnce in the pulse trigger mode, the output pulse width is Clear Mode: If ..
74LS240 ,Octal 3-STATE Buffer/Line Driver/Line ReceiverFeaturesYTypical power dissipation (enabled)YTRI-STATE outputs drive bus lines directlyInverting 13 ..
74LS241 ,Octal 3-STATE Buffer/Line Driver/Line ReceiverFeaturesYTypical power dissipation (enabled)YTRI-STATE outputs drive bus lines directlyInverting 13 ..
74LS244 ,Octal 3-STATE Buffer/Line Driver/Line ReceiverFeaturesThese buffers/line drivers are designed to improve both the 3-STATE outputs drive bus line ..
74LS245 ,3-STATE Octal Bus TransceiverFeaturesThese octal bus transceivers are designed for asynchro- Bi-Directional bus transceiver in ..
74LS247 ,8CD-to-Seven-Segment Decoders/Drivers(with 15V outputs)3SN74LS247LS247FUNCTION TABLEDECIMALINPUTS OUTPUTSOR OR BI/RBO BI/RBO NOTE NOTEFUNCTIONLT RBI D C B ..
78P2241-IGT , Transceiver
78P2344JAT-IGT , 4-port E3/DS3/STS-1 LIU with Jitter Attenuator
78P2344JAT-IGT , 4-port E3/DS3/STS-1 LIU with Jitter Attenuator
78P7200L-IGT , E3/DS3/STS-1 Transceiver
78Q2123 ,10/100 Fast Ethernet MicroPHYPin Description.......11 2.1 Legend...11 2.2 MII (Media Independent Interface) ....11 2.3 Control a ..
78Q2123/F ,10/100 Fast Ethernet MicroPHYapplications. The MDI isnegotiation and 10BASE-T signal receptionconnected to the line media via du ..
74LS221N
DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS
---Each multivibrator of the LS221 features a negative-transition-
triggered input and a positive-transition-triggered input either of
which can be used as an inhibit input.
Pulse triggering occurs at a voltage level and is not related to the
transition time of the input pulse. Schmitt-trigger input circuitry for B
input allows jitter-free triggering for inputs as slow as 1 volt/second,
providing the circuit with excellent noise immunity. A high immunity
to VCC noise is also provided by internal latching circuitry.
Once triggered, the outputs are independent of further transitions of
the inputs and are a function of the timing components. The output
pulses can be terminated by the overriding clear. Input pulse width
may be of any duration relative to the output pulse width. Output pulse
width may be varied from 35 nanoseconds to a maximum of 70 s by
choosing appropriate timing components. With Rext = 2.0 kΩ and Cext
= 0, a typical output pulse of 30 nanoseconds is achieved. Output rise
and fall times are independent of pulse length.
Pulse width stability is achieved through internal compensation and
is virtually independent of VCC and temperature. In most applications,
pulse stability will only be limited by the accuracy of external timing
components.
Jitter-free operation is maintained over the full temperature and VCC
ranges for greater than six decades of timing capacitance (10 pF to 10
μF), and greater than one decade of timing resistance (2.0 to 100 kΩ
for the SN74LS221). Pulse width is defined by the relationship:
tw(out) = CextRext ln 2.0 ≈ 0.7 Cext Rext; where tW is in ns if Cext is in
pF and Rext is in kΩ. If pulse cutoff is not critical, capacitance up to
1000 μF and resistance as low as 1.4 kΩ may be used. The range of
jitter-free pulse widths is extended if VCC is 5.0 V and 25°C
temperature. SN74LS221 is a Dual Highly Stable One-Shot Overriding Clear Terminates Output Pulse Pin Out is Identical to SN74LS123
GUARANTEED OPERATING RANGES
