74LS192 ,PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERLOGIC DIAGRAMSP P P P0 1 2 311 15 1 10 9PL(LOAD)5CPTCU 12U(UP COUNT)(CARRYOUTPUT)S S S SD D D DQ Q ..
74LS193 ,Synchronous Up/Down 4-bit Binary Counters(dual clock lines)General Descriptioninputs are buffered to lower the drive requirements of clockThe DM74LS193 circui ..
74LS194A ,LOW POWER SCHOTTKY
74LS195 ,4-bit Parallel-Access Shift RegistersLOGIC DIAGRAM** * * * * * * ** * * ** * * * * * * * * * * * * * * * * ** ** ** * * * * * * ** * ..
74LS195APC ,21 mA; universal 4-bit shift registerapplications by tying the two pins together. When thePTiinput is LOW, the '195 appears as
four com ..
74LS195APC ,21 mA; universal 4-bit shift registerapplications. It
performs serial, parallel, serial to parallel, or parallel to serial d_ata transf ..
78M18 , LINEAR INTEGRATED CIRCUITS 3-TERMINAL VOLATGE REGULATORS
78M18 , LINEAR INTEGRATED CIRCUITS 3-TERMINAL VOLATGE REGULATORS
78M6612-IGT/F ,Single-Phase, Dual-Outlet Power and Energy Measurement IC
78M6612-IMR/F/PD ,Single-Phase, Dual-Outlet Power and Energy Measurement IC
78P2241-IGT , Transceiver
78P2344JAT-IGT , 4-port E3/DS3/STS-1 LIU with Jitter Attenuator
74LS192-SN54LS193J-SN74LS193N
PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER
PRESETT ABLE BCD/DECADE
UP/DOWN COUNTER
PRESETT ABLE 4-BIT BINARY
UP/DOWN COUNTERThe SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the
SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate
Count Up and Count Down Clocks are used and in either counting mode the
circuits operate synchronously. The outputs change state synchronous with
the LOW-to-HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down outputs are
provided which are used as the clocks for a subsequent stages without extra
logic, thus simplifying multistage counter designs. Individual preset inputs
allow the circuits to be used as programmable counters. Both the Parallel
Load (PL) and the Master Reset (MR) inputs asynchronously override the
clocks. Low Power ... 95 mW Typical Dissipation High Speed... 40 MHz Typical Count Frequency Synchronous Counting Asynchronous Master Reset and Parallel Load Individual Preset Inputs Cascading Circuitry Internally Provided Input Clamp Diodes Limit High Speed Termination Effects
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
CONNECTION DIAGRAM DIP (TOP VIEW)VCC MR TCD TCU P2PL P3 Q0 CPD CPU Q2 Q3 GND
PIN NAMES LOADING (Note a)CPU
CPD
TCD
TCU
Count Up Clock Pulse Input
Count Down Clock Pulse Input
Asynchronous Master Reset (Clear) Input
Asynchronous Parallel Load (Active LOW) Input
Parallel Data Inputs
Flip-Flop Outputs (Note b)
Terminal Count Down (Borrow) Output (Note b)
Terminal Count Up (Carry) Output (Note b)
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
