74LS165 ,8-Bit Parallel In/Serial Output Shift RegistersFeaturesThis device is an 8-bit serial shift register which shifts data Complementary outputsin th ..
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74LS165
8-Bit Parallel In/Serial Output Shift Registers
DM74LS165 8-Bit Parallel In/Serial Output Shift Registers August 1986 Revised March 2000 DM74LS165 8-Bit Parallel In/Serial Output Shift Registers General Description Features This device is an 8-bit serial shift register which shifts data � Complementary outputs in the direction of Q toward Q when clocked. Parallel-in A H � Direct overriding (data) inputs access is made available by eight individual direct data � Gated clock inputs inputs, which are enabled by a low level at the shift/load � Parallel-to-serial data conversion input. These registers also feature gated clock inputs and � Typical frequency 35 MHz complementary outputs from the eighth bit. � Typical power dissipation 105 mW Clocking is accomplished through a 2-input NOR gate, per- mitting one input to be used as a clock-inhibit function. Holding either of the clock inputs HIGH inhibits clocking, and holding either clock input LOW with the load input HIGH enables the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is HIGH. Parallel loading is inhibited as long as the load input is HIGH. Data at the parallel inputs are loaded directly into the register on a HIGH-to-LOW transition of the shift/load input, regardless of the logic levels on the clock, clock inhibit, or serial inputs. Ordering Code: Order Number Package Number Package Description DM74LS165M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS165WM M16B 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS165N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Internal Shift/ Clock Clock Serial Parallel Outputs Output Load Inhibit A...H Q Q Q A B H L X X X a...h a b h HL L X X Q Q Q A0 B0 H0 HL ↑ HX HQ Q An Gn HL ↑ LX LQ Q An Gn HH X X X Q Q Q A0 B0 H0 H = HIGH Level (steady state) L = LOW Level (steady state) X = Don't Care (any input, including transitions) ↑ = Transition from LOW-to-HIGH level a...h = The level of steady-state input at inputs A through H, respectively. Q , Q , Q = The level of Q , Q , or Q , respectively, before the A0 B0 H0 A B H indicated steady-state input conditions were established. Q , Q = The level of Q or Q , respectively, before the most recent An Gn A G ↑ transition of the clock. © 2000 DS006399
