74LS160 ,Synchronous Decade Counters(direct clear)SN54/74LS160ASN54/74LS161ASN54/74LS162ABCD DECADE COUNTERS/SN54/74LS163A4-BIT BINARY COUNTERSThe LS ..
74LS161 ,Synchronous 4-Bit Binary CountersGeneral Descriptioncounters for n-bit synchronous
74LS161 ,Synchronous 4-Bit Binary CountersSN54/74LS160ASN54/74LS161ASN54/74LS162ABCD DECADE COUNTERS/SN54/74LS163A4-BIT BINARY COUNTERSThe LS ..
74LS161 ,Synchronous 4-Bit Binary CountersDM74LS161A • DM74LS163A Synchronous 4-Bit Binary CountersAugust 1986Revised April 2000DM74LS161A • ..
74LS161 ,Synchronous 4-Bit Binary CountersSN54/74LS160ASN54/74LS161ASN54/74LS162ABCD DECADE COUNTERS/SN54/74LS163A4-BIT BINARY COUNTERSThe LS ..
74LS16-1 ,Synchronous 4-Bit Binary Countersapplications without addi-These synchronous, presettable counters feature an inter-tional gating. I ..
78L15A , 3-Terminal Regulators
78L15A , 3-Terminal Regulators
78L15A , 3-Terminal Regulators
78L15AC , The Linear ICs Three-Terminal Low Current Positive Voltage Regulators
78L24 , LINEAR INTEGRATED CIRCUITS 3-TERMINAL VOLATGE REGULATORS
78L24 , LINEAR INTEGRATED CIRCUITS 3-TERMINAL VOLATGE REGULATORS
74LS160-74LS161-74LS162-SN54LS160J-SN54LS161J-SN54LS162J-SN54LS165J-SN74LS161N
Synchronous Decade Counters(direct clear)
BCD DECADE COUNTERS/
4-BIT BINARY COUNTERSThe LS160A/161A/162A/163A are high-speed 4-bit synchronous count-
ers. They are edge-triggered, synchronously presettable, and cascadable
MSI building blocks for counting, memory addressing, frequency division and
other applications. The LS160A and LS162A count modulo 10 (BCD). The
LS161A and LS163A count modulo 16 (binary.)
The LS160A and LS161A have an asynchronous Master Reset (Clear)
input that overrides, and is independent of, the clock and all other control
inputs. The LS162A and LS163A have a Synchronous Reset (Clear) input that
overrides all other control inputs, but is active only during the rising clock
edge. Synchronous Counting and Loading Two Count Enable Inputs for High Speed Synchronous Expansion Terminal Count Fully Decoded Edge-Triggered Operation Typical Count Rate of 35 MHz ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.--- -- -- --- --- -- -- -- --
*MR for LS160A and LS161A
*SR for LS162A and LS163A
PIN NAMES LOADING (Note a)P0–P3
CEP
CET
Q0–Q3
Parallel Enable (Active LOW) Input
Parallel Inputs
Count Enable Parallel Input
Count Enable Trickle Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Synchronous Reset (Active LOW) Input
Parallel Outputs (Note b)
Terminal Count Output (Note b)
NOTES: 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
