DM74LS09M ,Quad 2-Input AND Gates with Open-Collector OutputsDM74LS09 Quad 2-Input AND Gates with Open-Collector OutputsAugust 1986Revised March 2000DM74LS09Qua ..
DM74LS09M ,Quad 2-Input AND Gates with Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains four independent gates each of w ..
DM74LS09N ,Quad 2-Input AND Gates with Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains four independent gates each of w ..
DM74LS107AN ,Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary OutputsDM54LS107A/DM74LS107ADualNegative-Edge-TriggeredMaster-SlaveJ-KFlip-FlopswithClearandComplementaryO ..
DM74LS109AM ,Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary OutputsGeneral DescriptionThis device contains two independent positive-edge-trig-gered J-K flip-flops wit ..
DM74LS109AMX , Dual Positive Edge-Triggered J-K Flip-Flop with Preset Clear and Complementary OutputsDM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs ..
DS21348T+ ,3.3V E1/T1/J1 Line Interfaceapplications. The device can generate the necessary G.703 E1 waveshapes in 75Ω or 120Ω
DS21348T+ ,3.3V E1/T1/J1 Line Interfaceapplications and DSX-1 line build-outs or CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB fo ..
DS21348T+ ,3.3V E1/T1/J1 Line InterfaceFEATURES PIN CONFIGURATIONS 111 PRELMINARY Complete E1, T1, or J1 Line Interface Unit 44TOP VIEW ( ..
DS21348TN ,3.3V E1/T1/J1 line interfaceapplications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and ..
DS21348T-W ,3.3V E1/T1/J1 Line Interfaceapplications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and ..
DS21349DK ,T1/J1 Line Interface Unit Design Kit DS2149DK/DS21349DK T1/J1 Line Interface Unit Design Kit
74LS09-DM74LS09M-DM74LS09N
Quad 2-Input AND Gates with Open-Collector Outputs
DM74LS09 Quad 2-Input AND Gates with Open-Collector Outputs August 1986 Revised March 2000 DM74LS09 Quad 2-Input AND Gates with Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains four independent gates each of which performs the logic AND function. The open-collector out- puts require external pull-up resistors for proper logical operation. Where: N (I ) = total maximum output high current 1 OH for all outputs tied to pull-up resistor N (I ) = total maximum input high current for 2 IH all inputs tied to pull-up resistor N (I ) = total maximum input low current for 3 IL all inputs tied to pull-up resistor Ordering Code: Order Number Package Number Package Description DM74LS09M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS09N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Connection Diagram Function Table Y = AB Inputs Output AB Y LLL LH L HL L HHH H = HIGH Logic Level L = LOW Logic Level © 2000 DS006348
